Inventor

PEDERSEN BRUCE B

US141 patents

⚠️ This page may combine multiple inventors who share the name “PEDERSEN BRUCE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PEDERSEN BRUCE B

ALTERA CORP

Programmable logic device architecture with super-regions having logic regions and a memory region

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic array integrated circuit devices with interleaved logic array blocks

Programmable logic integrated circuits with partitioned logic element using shared lab-wide signals

Programmable logic array integrated circuit devices

Programmable logic array integrated circuits with enhanced output routing

Programmable logic array with local and global conductors

Look up table implementation of fast carry for adders and counters

Programmable logic array having local and long distance conductors

Programmable logic element interconnections for programmable logic array integrated circuits

High-density erasable programmable logic device architecture using multiplexer interconnections

Registered logic macrocell with product term allocation and adjacent product term stealing

Registered logic macrocell with product term allocation and adjacent product term stealing

Physically unclonable functions with enhanced margin testing

Programmable logic device with carry look-ahead

Programmable logic device configured to accommodate multiplication

Circuitry and methods for internal interconnection of programmable logic devices

Programmable logic device circuitry for improving multiplier speed and/or efficiency

Programmable logic device having combinational logic at inputs to logic elements within logic array blocks

Logic region resources for programmable logic devices

Programmable logic device architectures

Programmable logic array circuits comprising look up table implementation of fast carry adders and counters

Programmable logic array integrated circuit devices

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

Programmable logic device with hierarchical interconnection resources

Programmable logic device with redundant circuitry

Programmable logic device with redundant circuitry

Programmable logic array integrated circuit devices

Programmable logic device with hierarchical interconnection resources

Programmable logic array integrated circuits with enhanced cascade

Programmable logic array integrated circuits with enhanced cascade

Programmable logic array intergrated circuit devices

Logic cell for programmable logic devices

Programmable logic array integrated circuits with enhanced carry routing

Programmable logic array integrated circuits

High-density erasable programmable logic device architecture using multiplexer interconnections

Programmable logic device with multiplexer-based programmable interconnections

Method and apparatus for securing programming data of a programmable device

Partially reconfigurable memory cell arrays

Volatile memory elements with soft error upset immunity for programmable logic device integrated circuits

PCI-compatible programmable logic devices

Versatile RAM for programmable logic device

Programmable logic devices with enhanced multiplexing capabilities

Programmable logic device having quadrant layout

Programmable logic devices with enhanced multiplexing capabilities

Variable depth memories for programmable logic devices

Programmable logic array integrated circuit architectures

Routing in programmable logic devices using shared distributed programmable logic connectors

PEDERSEN BRUCE B

Differential power analysis resistant encryption and decryption functions

Setting security features of programmable logic devices