Inventor
YEH CHEN-NAN
TW45 patents
⚠️ This page may combine multiple inventors who share the name “YEH CHEN-NAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
23 patentsUS8048723B2Nov 1, 2011
Germanium FinFETs having dielectric punch-through stoppers
TAIWAN SEMICONDUCTOR MFG265 citations99
US7667271B2Feb 23, 2010
Fin field-effect transistors
TAIWAN SEMICONDUCTOR MFG583 citations99
US7612405B2Nov 3, 2009
Fabrication of FinFETs with multiple fin heights
TAIWAN SEMICONDUCTOR MFG55 citations98
US7560785B2Jul 14, 2009
Semiconductor device having multiple fin heights
TAIWAN SEMICONDUCTOR MFG59 citations98
US7939889B2May 10, 2011
Reducing resistance in source and drain regions of FinFETs
TAIWAN SEMICONDUCTOR MFG36 citations96
US7902035B2Mar 8, 2011
Semiconductor device having multiple fin heights
TAIWAN SEMICONDUCTOR MFG36 citations96
US7843000B2Nov 30, 2010
Semiconductor device having multiple fin heights
TAIWAN SEMICONDUCTOR MFG39 citations96
US9299785B2Mar 29, 2016
Reducing resistance in source and drain regions of FinFETs
TAIWAN SEMICONDUCTOR MFG12 citations93
US9076689B2Jul 7, 2015
Reducing resistance in source and drain regions of FinFETs
TAIWAN SEMICONDUCTOR MFG12 citations93
US7910994B2Mar 22, 2011
System and method for source/drain contact processing
TAIWAN SEMICONDUCTOR MFG21 citations93
US7880303B2Feb 1, 2011
Stacked contact with low aspect ratio
TAIWAN SEMICONDUCTOR MFG16 citations92
US6797630B1Sep 28, 2004
Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach
TAIWAN SEMICONDUCTOR MFG20 citations92
US7745890B2Jun 29, 2010
Hybrid metal fully silicided (FUSI) gate
TAIWAN SEMICONDUCTOR MFG11 citations84
US6616855B1Sep 9, 2003
Process to reduce surface roughness of low K damascene
TAIWAN SEMICONDUCTOR MFG13 citations84
US7029992B2Apr 18, 2006
Low oxygen content photoresist stripping process for low dielectric constant materials
TAIWAN SEMICONDUCTOR MFG9 citations73
US7629655B2Dec 8, 2009
Semiconductor device with multiple silicide regions
TAIWAN SEMICONDUCTOR MFG4 citations63
US7169701B2Jan 30, 2007
Dual damascene trench formation to avoid low-K dielectric damage
TAIWAN SEMICONDUCTOR MFG6 citations63
US7538025B2May 26, 2009
Dual damascene process flow for porous low-k materials
TAIWAN SEMICONDUCTOR MFG3 citations62
US7341943B2Mar 11, 2008
Post etch copper cleaning using dry plasma
TAIWAN SEMICONDUCTOR MFG6 citations60
US7977772B2Jul 12, 2011
Hybrid metal fully silicided (FUSI) gate
TAIWAN SEMICONDUCTOR MFG0 citations52
US7510940B2Mar 31, 2009
Method for fabricating dual-gate semiconductor device
TAIWAN SEMICONDUCTOR MFG0 citations52
US7892909B2Feb 22, 2011
Polysilicon gate formation by in-situ doping
TAIWAN SEMICONDUCTOR MFG0 citations42
US7094683B2Aug 22, 2006
Dual damascene method for ultra low K dielectrics
TAIWAN SEMICONDUCTOR MFG0 citations42
TAIWAN SEMICONDUCTOR MFG CO LTD
7 patentsUS10312327B2Jun 4, 2019
FinFETs having dielectric punch-through stoppers
TAIWAN SEMICONDUCTOR MFG CO LTD7 citations84
US9735042B2Aug 15, 2017
Dielectric punch-through stoppers for forming FinFETs having dual Fin heights
TAIWAN SEMICONDUCTOR MFG CO LTD10 citations84
US10269616B2Apr 23, 2019
Method of fabricating semiconductor device isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations73
US9722025B2Aug 1, 2017
FinFETs having dielectric punch-through stoppers
TAIWAN SEMICONDUCTOR MFG CO LTD3 citations73
US11133387B2Sep 28, 2021
FinFETs having dielectric punch-through stoppers
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations63
US9673082B2Jun 6, 2017
Method of fabricating semiconductor device isolation structure
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9601587B2Mar 21, 2017
Semiconductor device having elevated structure
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
YU CHEN-HUA
6 patentsUS8101994B2Jan 24, 2012
Semiconductor device having multiple fin heights
YU CHEN-HUA19 citations93
US8617948B2Dec 31, 2013
Reducing resistance in source and drain regions of FinFETs
YU CHEN-HUA8 citations84
US8143114B2Mar 27, 2012
System and method for source/drain contact processing
YU CHEN-HUA4 citations63
US8110890B2Feb 7, 2012
Method of fabricating semiconductor device isolation structure
YU CHEN-HUA2 citations63
US9224606B2Dec 29, 2015
Method of fabricating semiconductor device isolation structure
YU CHEN-HUA0 citations52
US8450200B2May 28, 2013
Method for stacked contact with low aspect ratio
YU CHEN-HUA0 citations52
CHANG CHENG-HUNG
4 patentsUS8106459B2Jan 31, 2012
FinFETs having dielectric punch-through stoppers
CHANG CHENG-HUNG97 citations99
US8957477B2Feb 17, 2015
Germanium FinFETs having dielectric punch-through stoppers
CHANG CHENG-HUNG23 citations92
US9230959B2Jan 5, 2016
FinFETs having dielectric punch-through stoppers
CHANG CHENG-HUNG10 citations84
US8883597B2Nov 11, 2014
Method of fabrication of a FinFET element
CHANG CHENG-HUNG13 citations82