Inventor

YU SHAOFENG

US53 patents

⚠️ This page may combine multiple inventors who share the name “YU SHAOFENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU SHAOFENG

TEXAS INSTRUMENTS INC

Method to improve SRAM performance and stability

Gate dielectric first replacement gate processes and integrated circuits therefrom

Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors

Gate dielectric first replacement gate processes and integrated circuits therefrom

Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same

Method for fabricating dual work function metal gates

Semiconductor device having a fully silicided gate electrode and method of manufacture therefor

Fabrication of transistors with a fully silicided gate electrode and channel strain

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Method of forming a fully silicided semiconductor device with independent gate and source/drain doping and related device

Method of enhancing drive current in a transistor

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

Method to obtain fully silicided poly gate

Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device

Method of forming silicided gates using buried metal layers

Method for manufacturing a silicided gate electrode using a buffer layer

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

CMOS process to improve SRAM yield

MOSFET with source side only stress

Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates

Method of forming source and drain regions utilizing dual capping layers and split thermal processes

INTEL CORP

Transistor gate electrode having conductor material layer

Transistor gate electrode having conductor material layer

Photosensitive device

Multi-level ring peer-to-peer network structure for peer and object discovery

Transistor gate electrode having conductor material layer

Photosensitive device

Reduced leakage trench isolation

Reduced leakage trench isolation

Photosensitive device

Transistor gate electrode having conductor material layer

SEMICONDUCTOR MFG INT SHANGHAI CORP

Semiconductor structure and fabrication method thereof, and static random access memory cell

Method for manufacturing a semiconductor device having a fin located on a substrate

Fin-type field effect transistor and manufacturing method thereof

Fin-type field effect transistor and manufacturing method thereof

Method of design rule check for off-grid irregular layout with on-grid design rule check deck

YU SHAOFENG

Asymmetric static random access memory cell with dual stress liner

CMOS process to improve SRAM yield

BENAISSA KAMEL

Low cost transistors using gate orientation and optimized implants

Low cost transistors using gate orientation and optimized implants

MEHRAD FREIDOON

Method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device

Structure for facilitating the simultaneous silicidation of a polysilicon gate and source/drain of a semiconductor device

MEHRAD FREIDO

Method for integration of replacement gate in CMOS flow

MURTHY ANAND

Transistor gate electrode having conductor material layer

SEMICONDUCTOR MFG INT CORP

CMOS devices and fabrication method

PINTO ANGELO

Integration scheme for changing crystal orientation in hybrid orientation technology (HOT) using direct silicon bonded (DSB) substrates

ZHEJIANG HUADIAN EQUIPMENT TESTING INST CO LTD

System and method for integrated test on primary-secondary pole-mounted breaker

DELTA ELECTRONICS (CHEN ZHOU) CO LTD

Electric connector, plug-in module thereof and method for manufacturing plug-in module