Inventor

JHA NIRAJ K

US30 patents

⚠️ This page may combine multiple inventors who share the name “JHA NIRAJ K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JHA NIRAJ K

UNIV PRINCETON

Design tools for high-level synthesis of a low-power data path

Secure optical communication channel for implantable medical devices

Method and system for neural network synthesis

System and method for security in Internet-of-Things and cyber-physical systems based on machine learning

System and method for energy efficient sensors with compression, artificial intelligence, and security

System and method for tracking a mobile device user

Stress detection and alleviation system and method

Vibration-based secure side channel for medical devices

System and method for graphical reticulated attack vectors for internet of things aggregate security (gravitas)

System and method for incremental learning using a grow-and-prune paradigm with neural networks

System and method for machine learning assisted security analysis of 5G network connected systems

System and method for wearable medical sensor and neural network based diabetes analysis

System and method for testing for SARS-COV-2/COVID-19 based on wearable medical sensors and neural networks

LUCENT TECHNOLOGIES INC

Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems

Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems

Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance

Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems

Concurrent hardware-software co-synthesis of hard real-time aperiodic and periodic specifications of embedded system architectures

Cluster-based hardware-software co-synthesis of heterogeneous distributed embedded systems

ZHANG WEI

Method and system for a run-time reconfigurable computer architecture

Hybrid nanotube/CMOS dynamically reconfigurable architecture and an integrated design optimization method and system therefor

Hybrid nanotube/CMOS dynamically reconfigurable architecture and system therefore

NEC USA INC

Constrained register sharing technique for low power VLSI design

Controller-based power management for low-power sequential circuits

NEC LAB AMERICA INC

System-level test architecture for delivery of compressed tests

Power estimation employing cycle-accurate functional descriptions

NEC CORP

Method for synthesis of common-case optimized circuits to improve performance and power dissipation

JHA NIRAJ K

Securing medical devices through wireless monitoring and anomaly detection

Mosenia Arsalan

Continuous authentication system and method based on BioAura

LIN TING-JUNG

Fine-grain dynamically reconfigurable FPGA architecture