Inventor

REDDY LAKSHMI N

US34 patents

⚠️ This page may combine multiple inventors who share the name “REDDY LAKSHMI N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REDDY LAKSHMI N

IBM

Time-driven placement and/or cloning of components for an integrated circuit

Physical synthesis optimization with fast metric check

Post-placement cell shifting

Time-driven placement and/or cloning of components for an integrated circuit

Memory element graph-based placement in integrated circuit design

Dynamic microprocessor gate design tool for area/timing margin control

Rule check heatmap prediction

Enhanced alignment for global placement in a circuit

Physical aware technology mapping in synthesis

Memory element graph-based placement in integrated circuit design

Time-driven placement and/or cloning of components for an integrated circuit

Multi-stage electronic design automation parameter tuning

Methods and systems for leveraging computer-aided design variability in synthesis tuning

Integrated circuit buffering solutions considering sink delays

Integrated circuit buffering solutions considering sink delays

Integrated circuit buffering solutions considering sink delays

Integrated circuit buffering solutions considering sink delays

Integrated circuit buffering solutions considering sink delays

Physical aware technology mapping in synthesis

Physical aware technology mapping in synthesis

Physical aware technology mapping in synthesis

Median line based critical timing path optimization

Virtual positive slack in physical synthesis

Virtual positive slack in physical synthesis

Task-based multi-process design synthesis

Time-driven placement and/or cloning of components for an integrated circuit

Time-driven placement and/or cloning of components for an integrated circuit

Multi-cycle latch tree synthesis

Routing layer re-optimization in physical synthesis

Dynamic microprocessor gate design tool for area/timing margin control

ALPERT CHARLES J

Post-placement cell shifting

Evaluating routing congestion based on average global edge congestion histograms

DRUMM ANTHONY D

Task-based multi-process design synthesis

Task-based multi-process design synthesis with reproducible transforms