Inventor

SAHA SOURAV

IN82 patents

⚠️ This page may combine multiple inventors who share the name “SAHA SOURAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAHA SOURAV

IBM

Integrated circuit design changes using through-silicon vias

Integrated circuit design changes using through-silicon vias

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Integrated circuit design changes using through-silicon vias

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Integrated circuit design changes using through-silicon vias

Creating regional routing blockages in integrated circuit design

Intra-run design decision process for circuit synthesis

Placement clustering-based white space reservation

Constraint-driven pin optimization for hierarchical design convergence

Critical region identification

Path-based congestion reduction in integrated circuit routing

Slack redistribution for additional power recovery

Computational thermal analysis during microchip design

Timing constraints formulation for highly replicated design modules

Timing constraints formulation for highly replicated design modules

Timing constraints formulation for highly replicated design modules

Circuit placement with electro-migration mitigation

Physical aware technology mapping in synthesis

Boundary based power guidance for physical synthesis

Boundary based power guidance for physical synthesis

Critical region identification

Thermally aware pin assignment and device placement

Congestion estimation techniques at pre-synthesis stage

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Area sharing between multiple large block synthesis (LBS) blocks

Global routing framework of integrated circuit based on localized routing optimization

Area sharing between multiple large block synthesis (LBS) blocks

Cross-hierarchy interconnect adjustment for power recovery

Physical aware technology mapping in synthesis

Physical aware technology mapping in synthesis

De-coupling capacitance placement

Cross-hierarchy interconnect adjustment for power recovery

De-coupling capacitance placement

Through-silicon via access device for integrated circuits

Cross-hierarchy interconnect adjustment for power recovery

COOPERVISION INT LTD

Methods of manufacturing an ophthalmic lens including asymmetric gradient index optical elements

Films having asymmetric grin optical elements for application to spectacles or other ophthalmic lenses

Ophthalmic lenses including asymmetric gradient index optical elements

Films having grin elements for application to spectacles or other ophthalmic lenses

Methods of manufacturing an ophthalmic lens

Dimpled contact lens

Contact lenses with microchannels

Contact lenses with microchannels

LSI CORP

System and method of hinted cache data removal

AVAGO TECH INT SALES PTE LID

Flexible write cache policy in RAID environments