Inventor

BLAND PATRICK M

US31 patents

⚠️ This page may combine multiple inventors who share the name “BLAND PATRICK M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BLAND PATRICK M

IBM

Arbitration logic for multiple bus computer system

PCI slot control apparatus with dynamic configuration for partitioned systems

System direct memory access (DMA) support logic for PCI based computer system

Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus

Data processing apparatus for dynamically setting timings in a dynamic memory system

USB-based networking and I/O hub

Bridge between two buses of a computer system with a direct memory access controller having a high address extension and a high count extension

Bridge for interfacing buses in computer system with a direct memory access controller having dynamically configurable direct memory access channels

Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses

Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer

Bridge for a power managed computer system with multiple buses and system arbitration

Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385

Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller

Method and apparatus for selectively posting write cycles using the 82385 cache controller

Providing independent clock failover for scalable blade servers

System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration

Powered conservation system in battery powered keyboard device including a microprocessor

Directing interrupts to currently idle processors

Microcomputer system employing address offset mechanism to increase the supported cache memory capacity

Data processing apparatus for selectively posting write cycles using the 82385 cache controller

Microprocessor hold and lock circuitry

Dual bus microcomputer system with programmable control of lock function

Bidirectional buffer with latch and parity capability

Memory downsizing in a computer memory subsystem

Method and apparatus for detecting a presence of a device

BLAND PATRICK M

Memory access to a dual in-line memory module form factor flash memory

Computer system including a page mode memory with decreased access time and method of operation thereof

Airflow barriers for efficient cooling of memory modules

INTEL CORP

CPU clock control unit

Method and apparatus for suspending and resuming a keyboard controller

Power management of DMA slaves with DMA traps