Inventor
PARKER DONALD D
US17 patents
⚠️ This page may combine multiple inventors who share the name “PARKER DONALD D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS6601121B2Jul 29, 2003
Quad pumped bus architecture and protocol
INTEL CORP104 citations99
US6041403AMar 21, 2000
Method and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstruction
INTEL CORP115 citations98
US6609171B1Aug 19, 2003
Quad pumped bus architecture and protocol
INTEL CORP34 citations96
US5600806AFeb 4, 1997
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
INTEL CORP50 citations96
US5586277ADec 17, 1996
Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
INTEL CORP56 citations96
US5630083AMay 13, 1997
Decoder for decoding multiple instructions in parallel
INTEL CORP88 citations95
US6907487B2Jun 14, 2005
Enhanced highly pipelined bus architecture
INTEL CORP22 citations93
US6880031B2Apr 12, 2005
Snoop phase in a highly pipelined bus architecture
INTEL CORP18 citations93
US6807592B2Oct 19, 2004
Quad pumped bus architecture and protocol
INTEL CORP16 citations93
US6804735B2Oct 12, 2004
Response and data phases in a highly pipelined bus architecture
INTEL CORP21 citations93
US5822555AOct 13, 1998
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
INTEL CORP22 citations92
US5581717ADec 3, 1996
Decoding circuit and method providing immediate data for a micro-operation issued from a decoder
INTEL CORP22 citations92
US5559974ASep 24, 1996
Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
INTEL CORP20 citations92
US5673427ASep 30, 1997
Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
INTEL CORP45 citations91
US5566298AOct 15, 1996
Method for state recovery during assist and restart in a decoder having an alias mechanism
INTEL CORP50 citations89
US5668985ASep 16, 1997
Decoder having a split queue system for processing intstructions in a first queue separate from their associated data processed in a second queue
INTEL CORP13 citations73