Inventor
BOYLE DOUGLAS B
US33 patents
⚠️ This page may combine multiple inventors who share the name “BOYLE DOUGLAS B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
22 patentsUS6155725ADec 5, 2000
Cell placement representation and transposition for integrated circuit physical design automation system
LSI LOGIC CORP174 citations99
US6092229AJul 18, 2000
Single chip systems using general purpose processors
LSI LOGIC CORP152 citations99
US5864854AJan 26, 1999
System and method for maintaining a shared cache look-up table
LSI LOGIC CORP243 citations99
US5761516AJun 2, 1998
Single chip multiprocessor architecture with internal task switching synchronization bus
LSI LOGIC CORP297 citations99
US5636125AJun 3, 1997
Computer implemented method for producing optimized cell placement for integrated circiut chip
LSI LOGIC CORP196 citations99
US5495419AFeb 27, 1996
Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
LSI LOGIC CORP199 citations99
US6493658B1Dec 10, 2002
Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
LSI LOGIC CORP104 citations98
US5875117AFeb 23, 1999
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
LSI LOGIC CORP91 citations98
US5557533ASep 17, 1996
Cell placement alteration apparatus for integrated circuit chip physical design automation system
LSI LOGIC CORP118 citations98
US5914887AJun 22, 1999
Congestion based cost factor computing apparatus for integrated circuit physical design automation system
LSI LOGIC CORP176 citations97
US6118870ASep 12, 2000
Microprocessor having instruction set extensions for decryption and multimedia applications
LSI LOGIC CORP82 citations96
US5963975AOct 5, 1999
Single chip integrated circuit distributed shared memory (DSM) and communications nodes
LSI LOGIC CORP55 citations96
US5903461AMay 11, 1999
Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows
LSI LOGIC CORP68 citations96
US5781439AJul 14, 1998
Method for producing integrated circuit chip having optimized cell placement
LSI LOGIC CORP33 citations96
US5745363AApr 28, 1998
Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations
LSI LOGIC CORP70 citations96
US5742510AApr 21, 1998
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
LSI LOGIC CORP61 citations96
US5682322AOct 28, 1997
Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method
LSI LOGIC CORP76 citations96
US5619419AApr 8, 1997
Method of cell placement for an itegrated circuit chip comprising integrated placement and cell overlap removal
LSI LOGIC CORP52 citations94
US5870313AFeb 9, 1999
Optimization processing for integrated circuit physical design automation system using parallel moving windows
LSI LOGIC CORP49 citations93
US5835378ANov 10, 1998
Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip
LSI LOGIC CORP24 citations93
US5815403ASep 29, 1998
Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
LSI LOGIC CORP45 citations93
US5793644AAug 11, 1998
Cell placement alteration apparatus for integrated circuit chip physical design automation system
LSI LOGIC CORP44 citations93
MONTEREY DESIGN SYSTEMS INC
5 patentsUS6557145B2Apr 29, 2003
Method for design optimization using logical and physical information
MONTEREY DESIGN SYSTEMS INC287 citations99
US6286128B1Sep 4, 2001
Method for design optimization using logical and physical information
MONTEREY DESIGN SYSTEMS INC202 citations95
US6099580AAug 8, 2000
Method for providing performance-driven logic optimization in an integrated circuit layout design
MONTEREY DESIGN SYSTEMS INC44 citations93
US6367051B1Apr 2, 2002
System and method for concurrent buffer insertion and placement of logic gates
MONTEREY DESIGN SYSTEMS INC31 citations90
US6385760B2May 7, 2002
System and method for concurrent placement of gates and associated wiring
MONTEREY DESIGN SYSTEMS INC9 citations73
MONTEREY DESIGN SYSTEMS
3 patentsUS6442743B1Aug 27, 2002
Placement method for integrated circuit design using topo-clustering
MONTEREY DESIGN SYSTEMS126 citations96
US6192508B1Feb 20, 2001
Method for logic optimization for improving timing and congestion during placement in integrated circuit design
MONTEREY DESIGN SYSTEMS23 citations91
US6449756B1Sep 10, 2002
Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design
MONTEREY DESIGN SYSTEMS13 citations71