Inventor
PARRELLA EUGENE L
US7 patents
Patents
7 patentsUS6246682B1Jun 12, 2001
Method and apparatus for managing multiple ATM cell queues
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Telecommunications framer utilizing state machine
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Real time debugger interface for embedded systems
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US6134653AOct 17, 2000
RISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unit
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US6765867B2Jul 20, 2004
Method and apparatus for avoiding head of line blocking in an ATM (asynchronous transfer mode) device
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US6205155B1Mar 20, 2001
Apparatus and method for limiting data bursts in ATM switch utilizing shared bus
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US5568060AOct 22, 1996
Circuit board insertion circuitry for high reliability backplanes
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