Inventor

DE VIVEK

US56 patents

⚠️ This page may combine multiple inventors who share the name “DE VIVEK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DE VIVEK

INTEL CORP

Floating-body DRAM using write word line for increased retention time

Level shifter

SRAM array with dynamic voltage for reducing active leakage power

Capacitor, method of increasing a capacitance area of same, and system containing same

Memory having bit line with resistor(s) between memory cells

Method and apparatus for leakage compensation with full Vcc pre-charge

Multiphase transformer for a multiphase DC-DC converter

Low-voltage, buffered bandgap reference with selectable output voltage

Differential, mixed swing, tristate driver circuit for high performance and low power on-chip interconnects

Non-linear clamp strength tuning method and apparatus

Stepwise drivers for DC/DC converters

Timing circuit for separate positive and negative edge placement in a switching DC-DC converter

Floating-body DRAM using write word line for increased retention time

Tri-rail domino circuit

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

Carbon nanotube fuse element

Error-detection flip-flop

Voltage regulation using digital voltage control

Memory cell bit valve loss detection and restoration

Sleep transistor array apparatus and method with leakage control circuitry

Device, system, and method to change a consistency of behavior by a cell circuit

Logic circuits using carbon nanotube transistors

Voltage regulator efficiency-aware global-minimum energy tracking

Multiple output voltage conversion

Physically unclonable function implemented with spin orbit coupling based magnetic memory

Master-slave controller architecture

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

Increasing the surface area of a memory cell capacitor

Multi-ported register files

Multiphase transformer for a multiphase DC-DC converter

Disabling cache portions during low voltage operations

Techniques in hybrid regulators of high power supply rejection ratio and conversion efficiency

System, apparatus and method for sensor-driven and heuristic-based minimum energy point tracking in a processor

Memory cell supply voltage control based on error detection

Controlling a processing performance level depending on energy expenditure

WILKERSON CHRISTOPHER

Disabling cache portions during low voltage operations

Disabling cache portions during low voltage operations

Disabling cache portions during low voltage operations

DOYLE BRIAN S

Capacitor, method of increasing a capacitance area of same, and system containing same

Increasing the surface area of a memory cell capacitor

KHELLAH MUHAMMAD

Memory cell supply voltage control based on error detection

Memory cell supply voltage control based on error detection

DE VIVEK

Circuits and methods for reducing minimum supply for register file cells

Circuits and methods for reducing minimum supply for register file cells

SCHROM GERHARD

DC-DC converter switching transistor current measurement technique

DC-DC converter switching transistor current measurement technique

KESHAVARZI ALI

Logic circuits using carbon nanotube transistors

BOWMAN KEITH

Sequential circuit with error detection

RAYCHOWDHURY ARIJIT

Spin transfer torque based memory elements for programmable device arrays

KHELLAH MUHAMMAD M

Reducing minimum operating voltage through hybrid cache design