Inventor

DONO CHIAKI

JP52 patents

⚠️ This page may combine multiple inventors who share the name “DONO CHIAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DONO CHIAKI

ELPIDA MEMORY INC

Semiconductor device

Redundancy architecture for repairing semiconductor memories

Semiconductor memory device having a refresh cycle changing circuit

Semiconductor device performing burst order control and data bus inversion

Semiconductor memory and memory module

Semiconductor device

Semiconductor memory device that requires refresh operations

Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device manufactured using the same

Method of verifying a semiconductor integrated circuit apparatus, which can sufficiently evaluate a reliability of a non-destructive fuse module after it is assembled

Semiconductor memory device having a main word-line layer disposed above a column selection line layer

Semiconductor device

Semiconductor device

Semiconductor storage device

Semiconductor memory device with refreshment control

Semiconductor memory device of hierarchy word type and sub word driver circuit

Semiconductor device using plural internal operation voltages and data processing system using the same

Semiconductor memory device

Semiconductor device

Semiconductor memory device having plural memory cell arrays

Logic circuit performing exclusive or operation and data processing system including the same

Semiconductor device and test method therefor

MICRON TECHNOLOGY INC

Semiconductor layered device with data bus

Semiconductor memory device

Apparatuses and methods for providing multiphase clock signals

Apparatuses and methods for direct access hybrid testing

Semiconductor device having a test circuit

Shared error detection and correction memory

Apparatuses and methods for fixing a logic level of an internal signal line

Apparatuses and methods for providing clocks to data paths

System and method for write data bus control in a stacked memory device

Shared error detection and correction memory

Apparatuses and methods for fixing a logic level of an internal signal line

Semiconductor layered device with data bus

Semiconductor memory device

Memory device with write data bus control

Apparatuses and methods for direct access hybrid testing

Apparatuses and methods for providing multiphase clock signals

Replication of a first interface onto a second interface and related systems, methods, and devices

Shared error detection and correction memory

Memory device with write data bus control

Multiple algorithmic pattern generator testing of a memory device

DONO CHIAKI

Semiconductor device having serializer converting parallel data into serial data to output serial data from output buffer circuit

Semiconductor memory device having pad electrodes arranged in plural rows

Semiconductor device including an anti-fuse element

Semiconductor device having output buffer circuit in which impedance thereof can be controlled

Semiconductor device and level shift circuit using the same

PS4 LUXCO SARL

Semiconductor storage device and system provided with same

Semiconductor device having latency counter to control output timing of data and data processing system including the same

HITACHI LTD

Semiconductor integrated circuit

Semiconductor integrated circuit