Inventor
LOIKO KONSTANTIN V
US27 patents
⚠️ This page may combine multiple inventors who share the name “LOIKO KONSTANTIN V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
FREESCALE SEMICONDUCTOR INC
12 patentsUS7521314B2Apr 21, 2009
Method for selective removal of a layer
FREESCALE SEMICONDUCTOR INC29 citations92
US7821055B2Oct 26, 2010
Stressed semiconductor device and method for making
FREESCALE SEMICONDUCTOR INC37 citations91
US7811886B2Oct 12, 2010
Split-gate thin film storage NVM cell with reduced load-up/trap-up effects
FREESCALE SEMICONDUCTOR INC33 citations91
US7799650B2Sep 21, 2010
Method for making a transistor with a stressor
FREESCALE SEMICONDUCTOR INC27 citations91
US8035156B2Oct 11, 2011
Split-gate non-volatile memory cell and method
FREESCALE SEMICONDUCTOR INC8 citations83
US7985649B1Jul 26, 2011
Method of making a semiconductor structure useful in making a split gate non-volatile memory cell
FREESCALE SEMICONDUCTOR INC18 citations83
US9548314B1Jan 17, 2017
Method of making a non-volatile memory (NVM) with trap-up reduction
FREESCALE SEMICONDUCTOR INC2 citations67
US9111867B2Aug 18, 2015
Split gate nanocrystal memory integration
FREESCALE SEMICONDUCTOR INC3 citations63
US7960243B2Jun 14, 2011
Method of forming a semiconductor device featuring a gate stressor and semiconductor device
FREESCALE SEMICONDUCTOR INC4 citations63
US7960267B2Jun 14, 2011
Method for making a stressed non-volatile memory device
FREESCALE SEMICONDUCTOR INC2 citations61
US9847397B2Dec 19, 2017
Method of forming split gate memory with improved reliability
FREESCALE SEMICONDUCTOR INC0 citations52
US10026820B2Jul 17, 2018
Split gate device with doped region and method therefor
FREESCALE SEMICONDUCTOR INC0 citations42
LOIKO KONSTANTIN V
6 patentsUS9343314B2May 17, 2016
Split gate nanocrystal memory integration
LOIKO KONSTANTIN V4 citations72
US9202930B2Dec 1, 2015
Memory with discrete storage elements
LOIKO KONSTANTIN V3 citations62
US8766362B2Jul 1, 2014
Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
LOIKO KONSTANTIN V2 citations61
US8236638B2Aug 7, 2012
Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner
LOIKO KONSTANTIN V3 citations61
US9331160B2May 3, 2016
Split-gate non-volatile memory cells having gap protection zones
LOIKO KONSTANTIN V0 citations49
US9257445B2Feb 9, 2016
Method of making a split gate non-volatile memory (NVM) cell and a logic transistor
LOIKO KONSTANTIN V0 citations41
CHARTERED SEMICONDUCTOR MFG
4 patentsUS6249035B1Jun 19, 2001
LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect
CHARTERED SEMICONDUCTOR MFG17 citations88
US5894059AApr 13, 1999
Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect
CHARTERED SEMICONDUCTOR MFG15 citations71
US6071793AJun 6, 2000
Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect
CHARTERED SEMICONDUCTOR MFG12 citations69
US6380610B1Apr 30, 2002
Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect
CHARTERED SEMICONDUCTOR MFG0 citations49
WINSTEAD BRIAN A
3 patentsUS8962416B1Feb 24, 2015
Split gate non-volatile memory cell
WINSTEAD BRIAN A3 citations62
US8587039B2Nov 19, 2013
Method of forming a semiconductor device featuring a gate stressor and semiconductor device
WINSTEAD BRIAN A2 citations62
US9379222B2Jun 28, 2016
Method of making a split gate non-volatile memory (NVM) cell
WINSTEAD BRIAN A0 citations41