Inventor

GOLLA ROBERT T

US64 patents

⚠️ This page may combine multiple inventors who share the name “GOLLA ROBERT T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOLLA ROBERT T

SUN MICROSYSTEMS INC

Handling cache misses by selectively flushing the pipeline

Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor

Fetch speculation in a multithreaded processor

Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor

Apparatus and method for fine-grained multithreading in a multipipelined processor core

Method and apparatus for power throttling in a multi-thread processor

Efficient utilization of a store buffer using counters

Thread-based clock enabling in a multi-threaded processor

Concurrent bypass to instruction buffers in a fine grain multithreaded processor

Minimal address state in a fine grain multithreaded processor

Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window

Software accessible fast VA to PA translation

Arbitration of window swap operations

GOLLA ROBERT T

Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations

Dynamic allocation of resources in a threaded, heterogeneous processor

Method and system for sharing functional units of a multithreaded processor

Logical map table for detecting dependency conditions between instructions having varying width operand values

Hybrid instruction buffer

Dependency matrix for the determination of load dependencies

Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions

Mechanism for selecting instructions for execution in a multithreaded processor

System and method for balancing instruction loads between multiple execution units using assignment history

Processor operating mode for mitigating dependency conditions between instructions having different operand sizes

IBM

Method and system for minimizing branch misprediction penalties within a processor

Method and system for recoding noneffective instructions within a data processing system

Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization

Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor

Method and system for recording noneffective instructions within a data processing system

Floating-point processor having post-writeback spill stage

ORACLE AMERICA INC

Delay slot handling in a processor

Apparatus and method for local operand bypassing for cryptographic instructions

Register access protocol in a multihreaded multi-core processor

Dynamic mitigation of thread hogs on a threaded processor

Memory with write port configured for double pump write

OLSON CHRISTOPHER H

Processor and method for implementing instruction support for hash algorithms

Processor and method for implementing instruction support for multiplication of large operands

Handling multi-cycle integer operations for a multi-threaded processor

CADENCE DESIGN SYSTEMS INC

Forced debug mode entry

Program thread selection between a plurality of execution pipelines

Instruction error handling

CHOU YUAN C

Branch misprediction recovery mechanism for microprocessors

Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss

WESTERN DIGITAL TECH INC

Cache diagnostic techniques

Removal of dependent instructions from an execution pipeline

GROHOSKI GREGORY F

System and method to manage address translation requests

Open Computing Trust I & II

Mechanism for selecting instructions for execution in a multithreaded processor

JORDAN PAUL J

Dynamic tag allocation in a multithreaded out-of-order processor

SPRACKLEN LAWRENCE A

Methods and mechanisms to support multiple features for a number of opcodes

SHAH MANISH K

Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor

ORACLE INT CORP

Multi-threaded instruction buffer design