Inventor
VASUDEVAN NALINI
US15 patents
⚠️ This page may combine multiple inventors who share the name “VASUDEVAN NALINI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
10 patentsUS9244677B2Jan 26, 2016
Loop vectorization methods and apparatus
INTEL CORP9 citations84
US9898266B2Feb 20, 2018
Loop vectorization methods and apparatus
INTEL CORP3 citations73
US10402177B2Sep 3, 2019
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP2 citations72
US9921832B2Mar 20, 2018
Instruction to reduce elements in a vector register with strided access pattern
INTEL CORP4 citations72
US9733913B2Aug 15, 2017
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP3 citations72
US9268541B2Feb 23, 2016
Methods and systems to vectorize scalar computer program loops having loop-carried dependences
INTEL CORP4 citations72
US9710279B2Jul 18, 2017
Method and apparatus for speculative vectorization
INTEL CORP1 citations52
US10372450B2Aug 6, 2019
Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate
INTEL CORP0 citations51
US9910650B2Mar 6, 2018
Method and apparatus for approximating detection of overlaps between memory ranges
INTEL CORP0 citations41
US9720667B2Aug 1, 2017
Automatic loop vectorization using hardware transactional memory
INTEL CORP0 citations41
BHARADWAJ JAYASHANKAR
3 patentsUS9798541B2Oct 24, 2017
Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register
BHARADWAJ JAYASHANKAR4 citations71
US9189236B2Nov 17, 2015
Speculative non-faulting loads and gathers
BHARADWAJ JAYASHANKAR0 citations50
US9268626B2Feb 23, 2016
Apparatus and method for vectorization with speculation support
BHARADWAJ JAYASHANKAR0 citations36