Inventor
MEHTA ASHOK
US23 patents
⚠️ This page may combine multiple inventors who share the name “MEHTA ASHOK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG CO LTD
10 patentsUS9646128B2May 9, 2017
System and method for validating stacked dies by comparing connections
TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US9552448B2Jan 24, 2017
Method and apparatus for electronic system model generation
TAIWAN SEMICONDUCTOR MFG CO LTD4 citations72
US11343433B2May 24, 2022
Image processing apparatus having overlapping sub-regions
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US11231767B2Jan 25, 2022
Dynamic frequency scaling
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations62
US10440281B2Oct 8, 2019
Image processing apparatus on integrated circuit and method thereof
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations52
US9514268B2Dec 6, 2016
Interposer defect coverage metric and method to maximize the same
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
US9404971B2Aug 2, 2016
Circuit and method for monolithic stacked integrated circuit testing
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations52
US9625971B2Apr 18, 2017
System and method of adaptive voltage frequency scaling
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations51
US9612277B2Apr 4, 2017
System and method for functional verification of multi-die 3D ICs
TAIWAN SEMICONDUCTOR MFG CO LTD1 citations51
US9047432B2Jun 2, 2015
System and method for validating stacked dies by comparing connections
TAIWAN SEMICONDUCTOR MFG CO LTD0 citations51
TAIWAN SEMICONDUCTOR MFG
4 patentsUS8826202B1Sep 2, 2014
Reducing design verification time while maximizing system functional coverage
TAIWAN SEMICONDUCTOR MFG22 citations92
US9110136B2Aug 18, 2015
Circuit and method for monolithic stacked integrated circuit testing
TAIWAN SEMICONDUCTOR MFG4 citations73
US9158881B2Oct 13, 2015
Interposer defect coverage metric and method to maximize the same
TAIWAN SEMICONDUCTOR MFG1 citations52
US8522177B2Aug 27, 2013
Method and apparatus for electronic system function verification at two levels
TAIWAN SEMICONDUCTOR MFG0 citations51
MEHTA ASHOK
4 patentsUS9015649B2Apr 21, 2015
Method and apparatus for electronic system model generation
MEHTA ASHOK6 citations82
US8402404B1Mar 19, 2013
Stacked die interconnect validation
MEHTA ASHOK10 citations82
US8578309B2Nov 5, 2013
Format conversion from value change dump (VCD) to universal verification methodology (UVM)
MEHTA ASHOK3 citations61
US8336009B2Dec 18, 2012
Method and apparatus for electronic system function verification at two levels
MEHTA ASHOK4 citations61
HUGHES AIRCRAFT CO
2 patentsUS5299198AMar 29, 1994
Method and apparatus for exploitation of voice inactivity to increase the capacity of a time division multiple access radio communications system
HUGHES AIRCRAFT CO178 citations98
US5678180AOct 14, 1997
Communication system and method providing dispatch and cellular interconnect communications
HUGHES AIRCRAFT CO13 citations71