Inventor

DUONG KENNETH

US52 patents

⚠️ This page may combine multiple inventors who share the name “DUONG KENNETH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUONG KENNETH

PERCEIVE CORP

Splitting neural network filters for implementation by neural network inference circuit

Computation of neural network node by neural network inference circuit

Reduced dot product computation circuit

Encoding of weight values stored on neural network inference circuit

Storage of input values within core of neural network inference circuit

Neural network inference circuit employing dynamic memory sleep

Weight value decoder of neural network inference circuit

Write cache for neural network inference circuit

Neural network inference circuit read controller with multiple operational modes

Input value cache for temporarily storing input values

Non-dot product computations on neural network inference circuit

Computation of neural network node with large input values

Control circuits for neural network inference circuit

Using quinary weights with neural network inference circuit designed for ternary weights

Time-multiplexed dot products for neural network inference circuit

Neural network inference circuit

Reduced-area circuit for dot product computation

Shifting input values within input buffer of neural network inference circuit

Data transfer for non-dot product computations on neural network inference circuit

Bus for transporting output values of a neural network layer to cores specified by configuration data

Reduced dot product computation circuit

Storage of input values across multiple cores of neural network inference circuit

Using lookup table to represent neural network activation function

Computation of neural network node

Reduced dot product computation circuit

Buffering of neural network inputs and outputs

Computation of neural network node by neural network inference circuit

Data transfer for non-dot product computations on neural network inference circuit

Weight value decoder of neural network inference circuit

Neural network inference circuit employing dynamic memory sleep

Allocating blocks of unified memory for integrated circuit executing neural network

XCELSIS CORP

Three dimensional circuit implementing machine trained network

Self repairing neural network

Back biasing of FD-SOI circuit blocks

Three dimensional chip structure implementing machine trained network

3D processor

3D Compute circuit with high density z-axis interconnects

3D compute circuit with high density Z-axis interconnects

Time borrowing between layers of a three dimensional chip stack

3D processor having stacked integrated circuit die

Systems and methods for inter-die block level design

Time borrowing between layers of a three dimensional chip stack

AMAZON TECH INC

Address decoding by neural network inference circuit read controller

Reduced dot product computation circuit

Computation of neural network node with large input values

ADEIA SEMICONDUCTOR INC

Three dimensional circuit implementing machine trained network

Three dimensional circuit implementing machine trained network

3D processor having stacked integrated circuit die

INTEL CORP

Memory circuitry with row-wise gating capabilities

Methods and apparatus for reusing lookup table random-access memory (LUTRAM) elements as configuration random-access memory (CRAM) elements