Inventor

SATISH NADATHUR RAJAGOPALAN

US61 patents

⚠️ This page may combine multiple inventors who share the name “SATISH NADATHUR RAJAGOPALAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SATISH NADATHUR RAJAGOPALAN

INTEL CORP

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Accelerator for sparse-dense matrix multiplication

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Neural network scheduling mechanism

Compute optimization mechanism for deep neural networks

Person tracking and privacy and acceleration of data using autonomous machines

Compute optimization mechanism

Gather and scatter operations in multi-level memory hierarchy

Accelerator for sparse-dense matrix multiplication

Compute optimization mechanism for deep neural networks

Dynamic distributed training of machine learning models

Graphics processing integrated circuit package

Hybrid graphics processor-field programmable gate array system

Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values

Compute optimization mechanism for deep neural networks

Compute optimization mechanism

Dynamic precision for neural network compute operations

Neural network optimization mechanism

Compute optimization mechanism for deep neural networks

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Graphics processing integrated circuit package

Compression mechanism

Accelerator for sparse-dense matrix multiplication

Neural network scheduling mechanism

Accelerator for sparse-dense matrix multiplication

Hardware prefetcher for indirect access patterns

Dynamic precision for neural network compute operations

Compute optimization mechanism

Compute optimization mechanism for deep neural networks

Dynamic precision for neural network compute operations

Targeted mapping of graphical data for compression

Storage management for machine learning at autonomous machines

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Compute optimization mechanism for deep neural networks

Compute optimization mechanism

Compute optimization mechanism

Search unit to accelerate variable length compression/decompression

Graphics processing integrated circuit package

Neural network scheduling mechanism

Neural network optimization mechanism

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

Neural network scheduling mechanism

Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values

HUGHES CHRISTOPHER J

Gather and scatter operations in multi-level memory hierarchy

Gather and scatter operations in multi-level memory hierarchy

CHHUGANI JATIN

Method and apparatus of instruction that merges and sorts smaller sorted vectors into larger sorted vector

META PLATFORMS INC

Reducing data transfer to machine learning accelerator hardware

KIM DAEHYUN

Method and apparatus for stream buffer management instructions