Inventor
WALLACE CHARLES H
US98 patents
⚠️ This page may combine multiple inventors who share the name “WALLACE CHARLES H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
36 patentsUS9666451B2May 30, 2017
Self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP45 citations98
US7632610B2Dec 15, 2009
Sub-resolution assist features
INTEL CORP179 citations98
US7569310B2Aug 4, 2009
Sub-resolution assist features for photolithography with trim ends
INTEL CORP168 citations95
US9793163B2Oct 17, 2017
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP28 citations94
US10892223B2Jan 12, 2021
Advanced lithography and self-assembled devices
INTEL CORP11 citations86
US10211088B2Feb 19, 2019
Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects
INTEL CORP11 citations84
US9793159B2Oct 17, 2017
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP13 citations84
US9005875B2Apr 14, 2015
Pre-patterned hard mask for ultrafast lithographic imaging
INTEL CORP12 citations84
US10409152B2Sep 10, 2019
Pattern decomposition lithography techniques
INTEL CORP4 citations83
US7915171B2Mar 29, 2011
Double patterning techniques and structures
INTEL CORP10 citations82
US7648803B2Jan 19, 2010
Diagonal corner-to-corner sub-resolution assist features for photolithography
INTEL CORP10 citations82
US10319625B2Jun 11, 2019
Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
INTEL CORP7 citations81
US12266708B2Apr 1, 2025
Integrated circuit structures having dielectric anchor void
INTEL CORP2 citations75
US12218052B2Feb 4, 2025
Advanced lithography and self-assembled devices
INTEL CORP1 citations75
US11854787B2Dec 26, 2023
Advanced lithography and self-assembled devices
INTEL CORP1 citations73
US11664274B2May 30, 2023
Method to repair edge placement errors in a semiconductor device
INTEL CORP2 citations73
US11373950B2Jun 28, 2022
Advanced lithography and self-assembled devices
INTEL CORP1 citations73
US10559529B2Feb 11, 2020
Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom
INTEL CORP6 citations73
US10297467B2May 21, 2019
Self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP2 citations73
US10204830B2Feb 12, 2019
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP3 citations73
US11107786B2Aug 31, 2021
Pattern decomposition lithography techniques
INTEL CORP2 citations72
US10490519B2Nov 26, 2019
Pattern decomposition lithography techniques
INTEL CORP2 citations72
US11145541B2Oct 12, 2021
Conductive via and metal line end fabrication and structures resulting therefrom
INTEL CORP5 citations71
US12557625B2Feb 17, 2026
Spacer self-aligned via structures using directed self assembly for gate contact or trench contact
INTEL CORP1 citations64
US12563774B2Feb 24, 2026
Integrated circuit structures with deep via structure
INTEL CORP0 citations63
US12501659B2Dec 16, 2025
Integrated circuit structures having dielectric anchor void
INTEL CORP0 citations63
US12408422B2Sep 2, 2025
Integrated circuit structures with backside gate cut or trench contact cut
INTEL CORP0 citations63
US12033894B2Jul 9, 2024
Gate aligned contact and method to fabricate same
INTEL CORP0 citations63
US11756829B2Sep 12, 2023
Gate aligned contact and method to fabricate same
INTEL CORP0 citations63
US11495496B2Nov 8, 2022
Gate aligned contact and method to fabricate same
INTEL CORP0 citations63
US10991599B2Apr 27, 2021
Self-aligned via and plug patterning for back end of line (BEOL) interconnects
INTEL CORP0 citations63
US10910265B2Feb 2, 2021
Gate aligned contact and method to fabricate same
INTEL CORP0 citations63
US12581927B2Mar 17, 2026
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication
INTEL CORP0 citations62
US12532538B2Jan 20, 2026
Integrated circuit structures having conductive structures in fin isolation regions
INTEL CORP0 citations62
US12453160B2Oct 21, 2025
Deep etch processing for transistors having varying pitch
INTEL CORP0 citations62
US12419085B2Sep 16, 2025
Integrated circuit structures having backside gate tie-down
INTEL CORP0 citations62
ITT
8 patentsUS4256569AMar 17, 1981
Arrangement to improve the optimization of the value of finished cuts in a livestock processing plant
ITT29 citations93
US4190100AFeb 26, 1980
Internal heat exchanger for meat
ITT24 citations82
US3940998AMar 2, 1976
Hog processing method
ITT26 citations76
US4179021ADec 18, 1979
Lift device arrangement
ITT9 citations74
US4118777AOct 3, 1978
Computer directed primal cut indicating device
ITT9 citations74
US4071957AFeb 7, 1978
Method and apparatus for measuring carcasses
ITT11 citations70
US3979835ASep 14, 1976
Method and apparatus for measuring carcasses
ITT18 citations70
US4228685AOct 21, 1980
Methods for computer assisted optimization of meat cuts from carcasses
ITT19 citations67
UNIV CALIFORNIA
3 patentsUS6479028B1Nov 12, 2002
Rapid synthesis of carbon nanotubes and carbon encapsulated metal nanoparticles by a displacement reaction
UNIV CALIFORNIA108 citations95
US6096282AAug 1, 2000
Instantaneous synthesis of refractory nitrides from solid precursors
UNIV CALIFORNIA18 citations82
US6120748ASep 19, 2000
Process for rapid solid-state formation of refractory nitrides
UNIV CALIFORNIA13 citations74
WALLACE CHARLES H
2 patentsGOLONZKA OLEG
1 patentShowing the top 50 of 98 patents by PatentIndex Score.