Inventor
HARAN MOHIT K
US30 patents
Patents
30 patentsUS10319625B2Jun 11, 2019
Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
INTEL CORP7 citations81
US11664274B2May 30, 2023
Method to repair edge placement errors in a semiconductor device
INTEL CORP2 citations73
US11145541B2Oct 12, 2021
Conductive via and metal line end fabrication and structures resulting therefrom
INTEL CORP5 citations71
US11393754B2Jul 19, 2022
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
INTEL CORP3 citations70
US12581927B2Mar 17, 2026
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication
INTEL CORP0 citations62
US12532538B2Jan 20, 2026
Integrated circuit structures having conductive structures in fin isolation regions
INTEL CORP0 citations62
US12419085B2Sep 16, 2025
Integrated circuit structures having backside gate tie-down
INTEL CORP0 citations62
US12400913B2Aug 26, 2025
Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication
INTEL CORP0 citations62
US12080639B2Sep 3, 2024
Contact over active gate structures with metal oxide layers to inhibit shorting
INTEL CORP1 citations62
US12598803B2Apr 7, 2026
Integrated circuit structures having gate cut offset
INTEL CORP0 citations61
US12527078B2Jan 13, 2026
Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation
INTEL CORP0 citations61
US12406931B2Sep 2, 2025
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
INTEL CORP0 citations60
US12261122B2Mar 25, 2025
Contact over active gate structures with etch stop layers for advanced integrated circuit structure fabrication
INTEL CORP0 citations60
US12237223B2Feb 25, 2025
Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication
INTEL CORP0 citations60
US11972979B2Apr 30, 2024
1D vertical edge blocking (VEB) via and plug
INTEL CORP0 citations60
US11721580B2Aug 8, 2023
1D vertical edge blocking (VEB) via and plug
INTEL CORP0 citations60
US12308284B2May 20, 2025
Plug and trench architectures for integrated circuits and methods of manufacture
INTEL CORP0 citations59
US11171043B2Nov 9, 2021
Plug and trench architectures for integrated circuits and methods of manufacture
INTEL CORP0 citations59
US12369392B2Jul 22, 2025
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates
INTEL CORP0 citations58
US11990472B2May 21, 2024
Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates
INTEL CORP0 citations58
US12002678B2Jun 4, 2024
Gate spacing in integrated circuit structures
INTEL CORP0 citations57
US11652045B2May 16, 2023
Via contact patterning method to increase edge placement error margin
INTEL CORP0 citations53
US11211324B2Dec 28, 2021
Via contact patterning method to increase edge placement error margin
INTEL CORP0 citations53
US12199161B2Jan 14, 2025
Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication
INTEL CORP0 citations52
US12471330B2Nov 11, 2025
Integrated circuit structures having maximized channel sizing
INTEL CORP0 citations51
US12154855B2Nov 26, 2024
Self-aligned patterning with colored blocking and structures resulting therefrom
INTEL CORP0 citations51
US12237388B2Feb 25, 2025
Transistor arrangements with stacked trench contacts and gate straps
INTEL CORP0 citations50
US10636700B2Apr 28, 2020
Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures
INTEL CORP0 citations49
US12310060B2May 20, 2025
Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances
INTEL CORP0 citations48
US12382721B2Aug 5, 2025
Integrated circuit structures having cut metal gates with dielectric spacer fill
INTEL CORP0 citations45