Inventor

WOODS WILLIAM E

US42 patents

⚠️ This page may combine multiple inventors who share the name “WOODS WILLIAM E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOODS WILLIAM E

HONEYWELL INF SYSTEMS

Trap mechanism for a data processing system

Apparatus for processing data transfer requests in a data processing system

Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories

Hit/miss logic for a cache memory

Queue structure for a data processing system

Multiple length address formation in a microprogrammed data processing system

Interrupt apparatus for enabling interrupt service in response to time out conditions

Word, byte and bit indexed addressing in a data processing system

Interrupt scan and processing system for a data processing system

Apparatus for changing the interrupt level of a process executing in a data processing system

Address formation in a microprogrammed data processing system

Address boundary detector

Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit

Instruction decoding logic system

Logic control system including cache memory for CPU-memory transfers

Logic control system for efficient memory to CPU transfers

Bus sourcing and shifter control of a central processing unit

Apparatus for performing the scientific add instruction

System providing adaptive response in information requesting unit

Architecture for a control store included in a data processing system

Transfer control technique between two units included in a data processing system

Two stage selection based on time of arrival and predetermined priority in a bus priority resolver

Logic transfer and decoding system

Flexible logic transfer and instruction decoding system

Buffer system for supply procedure words to a central processor unit

Control store test selection logic for a data processing system

Automatic operand length control of the result of a scientific arithmetic operation

Hardware demand fetch cycle system interface

BULL HN INFORMATION SYST

Method of optimizing the execution of program instuctions by an emulator using a plurality of execution units

Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories

Executing programs of a first system on a second system

Emulating the memory functions of a first system on a second system

State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections

Memory addressing arrangement

Data selection matrix

Apparatus and method for detecting a runaway firmware control unit

Buffered address stack register with parallel input registers and overflow protection

HONEYWELL BULL

BCD arithmetic using binary arithmetic and logical operations

Multifunction arithmetic indicator

Time partitioned bus arrangement

(unassigned)

Surveying rule assembly, and methods of constructing and utilizing same

HARRIS ROBERT J

Data processing system write protection mechanism