Inventor

HSUE CHEN-CHIU

TW97 patents

⚠️ This page may combine multiple inventors who share the name “HSUE CHEN-CHIU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSUE CHEN-CHIU

UNITED MICROELECTRONICS CORP

Process for fabricating a stacked capacitor

Multiple well device and process of manufacture

Process for creating high density integrated circuits utilizing double coating photoresist mask

ESD protection improvement

Method of fabricating an asymmetric lightly doped drain transistor device

Process for producing memory devices having narrow buried N+ lines

Method of forming a capacitor

Polycide bonding pad structure

Multiple cell with common bit line contact and method of manufacture thereof

Method of bonding an aluminum wire to an intergrated circuit bond pad

Method of making high coupling ratio NAND type flash memory

Self-aligned anti-punchthrough implantation process

Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors

Method for making fin-shaped stack capacitors on DRAM chips

Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices

Process for fabricating a stacked capacitor

Grounding method to eliminate the antenna effect in VLSI process

Process for self-align contact

Method of forming a stacked capacitor using sidewall spacers and local oxidation

Method of improvement ESD for LDD process

Process for fabricating double poly high density buried bit line mask ROM

Dram capacitor structure

Method for ESD protection improvement

Trench surrounded metal pattern

Method for forming a planar field oxide (fox) on substrates for integrated circuit

Method of implanting during manufacture of ROM device

Method of forming a DRAM stacked capacitor cell

Spin-on-glass planarization process with ion implantation

Trench surrounded metal pattern

Method of fabricating high density flat cell mask ROM

Top floating-gate flash EEPROM structure

High coupling ratio of flash memory

Method for fabricating flash memory cell having a decreased overlapped region between its source and gate

Method of making a blanket N-well structure for SRAM data stability in P-type substrates

Method for fabricating a local interconnection structure

Polysilicon programming memory cell

Double poly high density buried bit line mask ROM

SILICON INTEGRATED SYS CORP

Dual damascene process using metal hard mask

Method for forming selective protection layers on copper interconnects

Method for forming a metal capacitor in a damascene process

Dual damascene structure having capacitors

Method for forming a dual damascene structure having capacitors

Method for forming metal capacitors with a damascene process

Method for improving adhesion of a low k dielectric to a barrier layer

Method for fabricating metal capacitor

Method for forming a metal capacitor in a damascene process

Metal capacitors with damascene structures and method for forming the same

SILICON INTERGRATED SYSTEMS CO

Dual damascene process using an oxide liner for a dielectric barrier layer

POWERCHIP SEMICONDUCTOR CORP

Flash memory cell

UNITED MICROELECTRONICS COPORA

Planar field oxide isolation process for semiconductor integrated circuit devices using liquid phase deposition