Inventor
KERR DARREN
US18 patents
⚠️ This page may combine multiple inventors who share the name “KERR DARREN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH IND
12 patentsUS6101599AAug 8, 2000
System for context switching between processing elements in a pipeline of processing elements
CISCO TECH IND157 citations99
US6513108B1Jan 28, 2003
Programmable processing engine for efficiently processing transient data
CISCO TECH IND81 citations98
US6195739B1Feb 27, 2001
Method and apparatus for passing data among processor complex stages of a pipelined processing engine
CISCO TECH IND102 citations98
US6119215ASep 12, 2000
Synchronization and control system for an arrayed processing engine
CISCO TECH IND117 citations98
US6804815B1Oct 12, 2004
Sequence control mechanism for enabling out of order context processing
CISCO TECH IND89 citations97
US6173386B1Jan 9, 2001
Parallel processor with debug capability
CISCO TECH IND132 citations97
US6442669B2Aug 27, 2002
Architecture for a process complex of an arrayed pipelined processing engine
CISCO TECH IND52 citations96
US6272621B1Aug 7, 2001
Synchronization and control system for an arrayed processing engine
CISCO TECH IND71 citations96
US6965615B1Nov 15, 2005
Packet striping across a parallel header processor
CISCO TECH IND73 citations95
US6920562B1Jul 19, 2005
Tightly coupled software protocol decode with hardware data encryption
CISCO TECH IND36 citations92
US6986022B1Jan 10, 2006
Boundary synchronization mechanism for a processor of a systolic array
CISCO TECH IND11 citations83
US6836838B1Dec 28, 2004
Architecture for a processor complex of an arrayed pipelined processing engine
CISCO TECH IND12 citations74
CISCO TECH INC
5 patentsUS7100021B1Aug 29, 2006
Barrier synchronization mechanism for processors of a systolic array
CISCO TECH INC86 citations97
US7292578B1Nov 6, 2007
Flexible, high performance support for QoS on an arbitrary number of queues
CISCO TECH INC51 citations92
US7139899B2Nov 21, 2006
Selected register decode values for pipeline stage register addressing
CISCO TECH INC21 citations92
US7290105B1Oct 30, 2007
Zero overhead resource locks with attributes
CISCO TECH INC47 citations90
US7380101B2May 27, 2008
Architecture for a processor complex of an arrayed pipelined processing engine
CISCO TECH INC6 citations74