Inventor
LIANG CHUNLIN
US32 patents
Patents
32 patentsUS7022559B2Apr 4, 2006
MOSFET gate electrodes having performance tuned work functions and methods of making same
INTEL CORP216 citations99
US6492217B1Dec 10, 2002
Complementary metal gates and a process for implementation
INTEL CORP134 citations99
US6461895B1Oct 8, 2002
Process for making active interposer for high performance packaging applications
INTEL CORP353 citations99
US6373111B1Apr 16, 2002
Work function tuning for MOSFET gate electrodes
INTEL CORP181 citations99
US6130123AOct 10, 2000
Method for making a complementary metal gate electrode technology
INTEL CORP174 citations99
US5972758AOct 26, 1999
Pedestal isolated junction structure and method of manufacture
INTEL CORP233 citations99
US6696333B1Feb 24, 2004
Method of making integrated circuit with MOSFETs having bi-layer metal gate electrodes
INTEL CORP46 citations96
US6600364B1Jul 29, 2003
Active interposer technology for high performance CMOS packaging application
INTEL CORP74 citations96
US6365962B1Apr 2, 2002
Flip-chip on flex for high performance packaging applications
INTEL CORP47 citations96
US6265258B1Jul 24, 2001
Method for making a complementary metal gate electrode technology
INTEL CORP76 citations96
US6166417ADec 26, 2000
Complementary metal gates and a process for implementation
INTEL CORP82 citations96
US6022815AFeb 8, 2000
Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique
INTEL CORP61 citations96
US6743664B2Jun 1, 2004
Flip-chip on flex for high performance packaging applications
INTEL CORP45 citations95
US6998357B2Feb 14, 2006
High dielectric constant metal oxide gate dielectrics
INTEL CORP13 citations93
US6528856B1Mar 4, 2003
High dielectric constant metal oxide gate dielectrics
INTEL CORP22 citations93
US6222254B1Apr 24, 2001
Thermal conducting trench in a semiconductor structure and method for forming the same
INTEL CORP24 citations93
US7045468B2May 16, 2006
Isolated junction structure and method of manufacture
INTEL CORP28 citations92
US6879009B2Apr 12, 2005
Integrated circuit with MOSFETS having bi-layer metal gate electrodes
INTEL CORP27 citations92
US6794232B2Sep 21, 2004
Method of making MOSFET gate electrodes with tuned work function
INTEL CORP29 citations92
US6790731B2Sep 14, 2004
Method for tuning a work function for MOSFET gate electrodes
INTEL CORP21 citations92
US6642557B2Nov 4, 2003
Isolated junction structure for a MOSFET
INTEL CORP22 citations92
US6605845B1Aug 12, 2003
Asymmetric MOSFET using spacer gate technique
INTEL CORP30 citations92
US6180502B1Jan 30, 2001
Self-aligned process for making asymmetric MOSFET using spacer gate technique
INTEL CORP30 citations92
US5888897AMar 30, 1999
Process for forming an integrated structure comprising a self-aligned via/contact and interconnect
INTEL CORP52 citations92
US6362078B1Mar 26, 2002
Dynamic threshold voltage device and methods for fabricating dynamic threshold voltage devices
INTEL CORP15 citations84
US7187044B2Mar 6, 2007
Complementary metal gate electrode technology
INTEL CORP6 citations74
US7067406B2Jun 27, 2006
Thermal conducting trench in a semiconductor structure and method for forming the same
INTEL CORP7 citations74
US6624045B2Sep 23, 2003
Thermal conducting trench in a seminconductor structure and method for forming the same
INTEL CORP6 citations74
US6207541B1Mar 27, 2001
Method employing silicon nitride spacers for making an integrated circuit device
INTEL CORP8 citations72
US6133128AOct 17, 2000
Method for patterning polysilicon gate layer based on a photodefinable hard mask process
INTEL CORP5 citations72
US7223992B2May 29, 2007
Thermal conducting trench in a semiconductor structure
INTEL CORP2 citations63
US6689702B2Feb 10, 2004
High dielectric constant metal oxide gate dielectrics
INTEL CORP1 citations63