Inventor
KURTS TSVIKA
IL37 patents
⚠️ This page may combine multiple inventors who share the name “KURTS TSVIKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
34 patentsUS5392285AFeb 21, 1995
Cascading twisted pair ethernet hubs by designating one hub as a master and designating all other hubs as slaves
INTEL CORP62 citations96
US5351241ASep 27, 1994
Twisted pair ethernet hub for a star local area network
INTEL CORP72 citations96
US9910475B2Mar 6, 2018
Processor core power event tracing
INTEL CORP47 citations93
US7401241B2Jul 15, 2008
Controlling standby power of low power devices
INTEL CORP19 citations92
US6209053B1Mar 27, 2001
Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system
INTEL CORP26 citations92
US7363523B2Apr 22, 2008
Method and apparatus for controlling power management state transitions
INTEL CORP41 citations91
US6647545B1Nov 11, 2003
Method and apparatus for branch trace message scheme
INTEL CORP21 citations91
US6463554B1Oct 8, 2002
Bus patcher
INTEL CORP27 citations91
US5819027AOct 6, 1998
Bus patcher
INTEL CORP36 citations91
US7230450B2Jun 12, 2007
Programming semiconductor dies for pin map compatibility
INTEL CORP15 citations90
US6842035B2Jan 11, 2005
Apparatus and method for bus signal termination compensation during detected quiet cycle
INTEL CORP29 citations89
US6331957B1Dec 18, 2001
Integrated breakpoint detector and associated multi-level breakpoint techniques
INTEL CORP29 citations87
US9262163B2Feb 16, 2016
Real time instruction trace processors, methods, and systems
INTEL CORP5 citations84
US7529955B2May 5, 2009
Dynamic bus parking
INTEL CORP12 citations84
US7152167B2Dec 19, 2006
Apparatus and method for data bus power control
INTEL CORP16 citations83
US7227377B2Jun 5, 2007
Apparatus and method for bus signal termination compensation during detected quiet cycle
INTEL CORP14 citations81
US9660799B1May 23, 2017
Changing the clock frequency of a computing device
INTEL CORP4 citations71
US10725848B2Jul 28, 2020
Supporting hang detection and data recovery in microprocessor systems
INTEL CORP5 citations70
US11754623B2Sep 12, 2023
Systems and methods for intellectual property-secured, remote debugging
INTEL CORP3 citations69
US11085964B2Aug 10, 2021
Systems and methods for intellectual property-secured, remote debugging
INTEL CORP3 citations69
US11544174B2Jan 3, 2023
Method and apparatus for protecting trace data of a remote debug session
INTEL CORP5 citations67
US7222254B2May 22, 2007
System and method for over-clocking detection of a processor utilizing a feedback clock rate setting
INTEL CORP6 citations63
US7590913B2Sep 15, 2009
Method and apparatus of reporting memory bit correction
INTEL CORP2 citations62
US7216240B2May 8, 2007
Apparatus and method for address bus power control
INTEL CORP5 citations62
US7504856B2Mar 17, 2009
Programming semiconductor dies for pin map compatibility
INTEL CORP2 citations60
US9716646B2Jul 25, 2017
Using thresholds to gate timing packet generation in a tracing system
INTEL CORP0 citations52
US9696997B2Jul 4, 2017
Real time instruction trace processors, methods, and systems
INTEL CORP0 citations52
US8015365B2Sep 6, 2011
Reducing back invalidation transactions from a snoop filter
INTEL CORP1 citations52
US7877666B2Jan 25, 2011
Tracking health of integrated circuit structures
INTEL CORP1 citations52
US10656697B2May 19, 2020
Processor core power event tracing
INTEL CORP0 citations47
US12130724B2Oct 29, 2024
Closed chassis debugging through tunneling
INTEL CORP0 citations44
US10372642B2Aug 6, 2019
System, apparatus and method for performing distributed arbitration
INTEL CORP0 citations42
US10628542B2Apr 21, 2020
Core-only system management interrupt
INTEL CORP0 citations41
US9870301B2Jan 16, 2018
High-speed debug port using standard platform connectivity
INTEL CORP0 citations34