Inventor
SU JASON T
US21 patents
⚠️ This page may combine multiple inventors who share the name “SU JASON T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
6 patentsUS7639057B1Dec 29, 2009
Clock gater system
MARVELL INT LTD31 citations92
US7835217B1Nov 16, 2010
Write-assist and power-down circuit for low power SRAM applications
MARVELL INT LTD15 citations91
US7596012B1Sep 29, 2009
Write-assist and power-down circuit for low power SRAM applications
MARVELL INT LTD26 citations91
US8582387B1Nov 12, 2013
Method and apparatus for supplying power to a static random access memory (SRAM) cell
MARVELL INT LTD8 citations82
US7848173B1Dec 7, 2010
Address decoder
MARVELL INT LTD7 citations73
US7990199B1Aug 2, 2011
Clock gater system
MARVELL INT LTD0 citations51
SU JASON T
5 patentsUS8310894B1Nov 13, 2012
Write-assist and power-down circuit for low power SRAM applications
SU JASON T15 citations90
US8164972B1Apr 24, 2012
Address decoder
SU JASON T13 citations82
US10925794B2Feb 23, 2021
Stationary massage device, system and methods for soft tissue strain release
SU JASON T0 citations61
US8451041B2May 28, 2013
Charge-injection sense-amp logic
SU JASON T3 citations56
US8689162B2Apr 1, 2014
Method and apparatus for timing closure
SU JASON T1 citations51
MARVELL WORLD TRADE LTD
4 patentsUS8526257B2Sep 3, 2013
Processor with memory delayed bit line precharging
MARVELL WORLD TRADE LTD2 citations61
US8027218B2Sep 27, 2011
Processor instruction cache with dual-read modes
MARVELL WORLD TRADE LTD3 citations61
US9223920B2Dec 29, 2015
Method and apparatus for timing closure
MARVELL WORLD TRADE LTD1 citations52
US7787324B2Aug 31, 2010
Processor instruction cache with dual-read modes
MARVELL WORLD TRADE LTD0 citations51