Inventor
SUTERA MASSIMO
US14 patents
⚠️ This page may combine multiple inventors who share the name “SUTERA MASSIMO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AMPERE COMPUTING LLC
6 patentsUS12204410B2Jan 21, 2025
Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization
AMPERE COMPUTING LLC14 citations85
US12314130B2May 27, 2025
Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
AMPERE COMPUTING LLC0 citations61
US11934263B2Mar 19, 2024
Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization
AMPERE COMPUTING LLC1 citations61
US12474848B2Nov 18, 2025
Techniques for memory resource control using memory resource partitioning and monitoring
AMPERE COMPUTING LLC0 citations59
US12159056B2Dec 3, 2024
Extending functionality of memory controllers in a processor-based device
AMPERE COMPUTING LLC0 citations51
US12451206B2Oct 21, 2025
Extending functionality of memory controllers using a loopback mode for testing in a processor-based device
AMPERE COMPUTING LLC0 citations45
INTEL CORP
5 patentsUS9734054B1Aug 15, 2017
Efficient implementation of geometric series
INTEL CORP2 citations71
US10042562B2Aug 7, 2018
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
INTEL CORP0 citations51
US10007606B2Jun 26, 2018
Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory
INTEL CORP0 citations51
US9747041B2Aug 29, 2017
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
INTEL CORP0 citations51
US10162750B2Dec 25, 2018
System address reconstruction
INTEL CORP0 citations40