Inventor

SUNG MIN-GYU

KR191 patents

⚠️ This page may combine multiple inventors who share the name “SUNG MIN-GYU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUNG MIN-GYU

GLOBALFOUNDRIES INC

Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure

Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Integrated circuit structure incorporating multiple gate-all-around field effect transistors having different drive currents and method

Nanosheet field-effect transistor with full dielectric isolation

Self-aligned wrap-around contacts for nanosheet devices

Method and structure of forming self-aligned RMG gate for VFET

Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products

Vertical field effect transistor formation with critical dimension control

Fin cut with alternating two color fin hardmask

Methods of forming a gate contact for a semiconductor device above the active region

Single and double diffusion breaks on integrated circuit products comprised of FinFET devices

Gate cut method for replacement metal gate integration

Method of forming inner spacers on a nano-sheet/wire device

Method of controlling VFET channel length

Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devices

Dual thick EG oxide integration under aggressive SG fin pitch

Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers

Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay mark

Methods for selectively removing a fin when forming FinFET devices

Semiconductor device with a gate contact positioned above the active region

Methods for forming FinFETS having a capping layer for reducing punch through leakage

Methods of forming gate structure of semiconductor devices and the resulting devices

Fin liner integration under aggressive pitch

Replacement metal gate patterning for nanosheet devices

Self-aligned gate cut isolation

Dual mandrels to enable variable fin pitch

Air-gap spacers for field-effect transistors

Fin-type field effect transistors (FINFETS) with replacement metal gates and methods

Methods of forming a gate contact for a transistor above the active region and an air gap adjacent the gate of the transistor

Methods, apparatus and system for forming source/drain contacts using early trench silicide cut

Gate cuts after metal gate formation

Method of forming a semiconductor device with a gate contact positioned above the active region

Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures

Methods of forming integrated circuit structure using extreme ultraviolet photolithography technique and related integrated circuit structure

Methods of forming an air-gap spacer on a semiconductor device and the resulting device

Methods of forming gate electrodes on a vertical transistor device

Hybrid fin cutting processes for FinFET semiconductor devices

Dual liner CMOS integration methods for FinFET devices

Hybrid fin cut etching processes for products comprising tapered and non-tapered FinFET semiconductor devices

Methods, apparatus and system for local isolation formation for finFET devices

Formation of semiconductor structures employing selective removal of fins

Methods of forming self-aligned device level contact structures

Methods for forming FinFETS having a capping layer for reducing punch through leakage

Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices

Methods for forming transistor devices with different source/drain contact liners and the resulting devices

Methods for forming transistor devices with different threshold voltages and the resulting devices

Methods of forming fins for FinFET semiconductor devices and the resulting devices

IBM

Uniform bottom spacers in vertical field effect transistors

HYNIX SEMICONDUCTOR INC

Semiconductor device with vertical channel transistor and method for fabricating the same

VARIAN SEMICONDUCTOR EQUIPMENT ASS INC

Techniques for improved spacer in nanosheet device