P

Inventor

GREENFIELD ZVIKA

IL30 patents
⚠️ This page may combine multiple inventors who share the name “GREENFIELD ZVIKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

21 patents
US10210925B2Feb 19, 2019

Row hammer refresh command

INTEL CORP75 citations98
US9865326B2Jan 9, 2018

Row hammer refresh command

INTEL CORP83 citations98
US9747971B2Aug 29, 2017

Row hammer refresh command

INTEL CORP84 citations98
US9251885B2Feb 2, 2016

Throttling support for row-hammer counters

INTEL CORP68 citations97
US9026725B2May 5, 2015

Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals

INTEL CORP20 citations88
US9734079B2Aug 15, 2017

Hybrid exclusive multi-level memory architecture with memory management

INTEL CORP9 citations83
US10176099B2Jan 8, 2019

Using data pattern to mark cache lines as invalid

INTEL CORP3 citations71
US11036412B2Jun 15, 2021

Dynamically changing between latency-focused read operation and bandwidth-focused read operation

INTEL CORP3 citations70
US10204047B2Feb 12, 2019

Memory controller for multi-level system memory with coherency unit

INTEL CORP2 citations70
US10915453B2Feb 9, 2021

Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures

INTEL CORP0 citations61
US10949356B2Mar 16, 2021

Fast page fault handling process implemented on persistent memory

INTEL CORP0 citations59
US12591515B2Mar 31, 2026

Reducing memory power usage in far memory

INTEL CORP0 citations58
US9424198B2Aug 23, 2016

Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory

INTEL CORP1 citations52
US10657058B2May 19, 2020

Interleaved cache controllers with shared metadata and related devices and systems

INTEL CORP0 citations51
US10558570B2Feb 11, 2020

Concurrent accesses of asymmetrical memory sources

INTEL CORP0 citations51
US9582430B2Feb 28, 2017

Asymmetric set combined cache

INTEL CORP1 citations51
US11188467B2Nov 30, 2021

Multi-level system memory with near memory capable of storing compressed cache lines

INTEL CORP0 citations50
US10241916B2Mar 26, 2019

Sparse superline removal

INTEL CORP0 citations41
US10304418B2May 28, 2019

Operating system transparent system memory abandonment

INTEL CORP0 citations40
US9767041B2Sep 19, 2017

Managing sectored cache

INTEL CORP0 citations37
US10678706B2Jun 9, 2020

Cache memory with scrubber logic

INTEL CORP0 citations31

BAINS KULJIT S

2 patents

GREENFIELD ZVIKA

1 patent

BAINS KULJIT

1 patent

GUERON SHAY

1 patent

MOZAK CHRISTOPHER P

1 patent

SPRY BRYAN L

1 patent

ANANTARAMAN ARAVINDH V

1 patent

BONEN NADAV

1 patent