Inventor

FARABOSCHI PAOLO

US77 patents

⚠️ This page may combine multiple inventors who share the name “FARABOSCHI PAOLO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FARABOSCHI PAOLO

HEWLETT PACKARD ENTPR DEV LP

Tunable and dynamically adjustable error correction for memristor crossbars

Acceleration of model/weight programming in memristor crossbar arrays

Methods and systems for computing in memory

Memory network with memory nodes controlling memory accesses in the memory network

Memory integrity checking

Firewall to determine access to a portion of memory

Checkpoint generation

Memory side accelerator thread assignments

Independent shared and process virtual address translations

Acceleration of model/weight programming in memristor crossbar arrays

Optimal dispatching of Function-as-a-Service in heterogeneous accelerator environments

Optimal dispatching of function-as-a-service in heterogeneous accelerator environments

Methods and systems for computing in memory

Retrieve data block from determined devices

Data write to subset of memory devices

Using a directory-based cache coherence system to regulate snooping

Tracking errors associated with memory access operations

Floating point data set compression

Reallocate memory pending queue based on stall

Resilient fully sharded data parallel

Resilient optimizer states for fully sharded data parallel

Adjustable precision for multi-stage compute processes

HEWLETT PACKARD DEVELOPMENT CO

Synchronization of asynchronous emulated interrupts

Transparent remote data storage device and method

Memory network to route memory traffic and I/O traffic

Balancing the allocation of virtual machines in cloud systems

Networked client-server architecture for transparently transforming and executing applications

Simulation of system execution of instructions

Products with data-encoding pattern

HEWLETT PACKARD CO

Method for storing and decoding instructions for a microprocessor having a plurality of function units

Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs

Data cache for use with streaming data

Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures

Method and apparatus for protecting memory-mapped devices from side effects of speculative instructions

System and method for encoding constant operands in a wide issue processor

FARABOSCHI PAOLO

Managing a memory segment using a memory virtual appliance

Securing non-volatile memory regions

Remote connection between intermediary device and computing device via central authority software

Modifying length of synchronization quanta of simulation time in which execution of nodes is simulated

ST MICROELECTRONICS INC

System and method for executing variable latency load operations in a date processor

Executing conditional branch instructions in a data processor having a clustered architecture

Circuit and method for supporting misaligned accesses in the presence of speculative load instructions

Circuit and method for hardware-assisted software flushing of data and instruction caches

MOGUL JEFFREY CLIFFORD

Main memory with non-volatile memory and DRAM

ORTEGA DANIEL

Automated document processing system

SAMPER AYOSE FALCON

Simulating an application during a sampling period and a non-sampling period

HEWLETT PACKARD DEVELOPMENT CO LP

Memory node error correction

GUPTA ABHISHEK

Mapping high-performance computing applications to platforms

SGS THOMSON MICROELECTRONICS

Systems for loading unaligned words and methods of operating the same

YACOUB SHERIF

Method for finding text reading order in a document