Inventor
HICKS DWAIN A
US19 patents
Patents
19 patentsUS5584013ADec 10, 1996
Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
IBM88 citations96
US7302527B2Nov 27, 2007
Systems and methods for executing load instructions that avoid order violations
IBM47 citations92
US5694573ADec 2, 1997
Shared L2 support for inclusion property in split L1 data and instruction caches
IBM37 citations92
US5581734ADec 3, 1996
Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
IBM82 citations91
US10740248B2Aug 11, 2020
Methods and systems for predicting virtual address
IBM10 citations84
US10621106B1Apr 14, 2020
Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)
IBM7 citations84
US11221963B2Jan 11, 2022
Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB)
IBM2 citations73
US11061810B2Jul 13, 2021
Virtual cache mechanism for program break point register exception handling
IBM3 citations73
US10915459B2Feb 9, 2021
Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes
IBM2 citations73
US7376816B2May 20, 2008
Method and systems for executing load instructions that achieve sequential load consistency
IBM8 citations73
US5692151ANov 25, 1997
High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address
IBM13 citations73
US11409663B2Aug 9, 2022
Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes
IBM0 citations62
US7730290B2Jun 1, 2010
Systems for executing load instructions that achieve sequential load consistency
IBM2 citations62
US11157415B2Oct 26, 2021
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations61
US10649778B1May 12, 2020
Performance optimized congruence class matching for multiple concurrent radix translations
IBM1 citations58
US10824494B2Nov 3, 2020
Operation of a multi-slice processor implementing exception handling in a nested translation environment
IBM0 citations51
US10534715B2Jan 14, 2020
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations51
US10042691B2Aug 7, 2018
Operation of a multi-slice processor implementing exception handling in a nested translation environment
IBM0 citations51
US6604173B1Aug 5, 2003
System for controlling access to external cache memories of differing size
IBM0 citations51