Inventor
ROHRBAUGH III GEORGE W
US19 patents
Patents
19 patentsUS7444609B2Oct 28, 2008
Method of optimizing customizable filler cells in an integrated circuit physical design process
IBM207 citations97
US10671394B2Jun 2, 2020
Prefetch stream allocation for multithreading systems
IBM9 citations80
US10191847B2Jan 29, 2019
Prefetch performance
IBM2 citations73
US11520585B2Dec 6, 2022
Prefetch store preallocation in an effective address-based cache directory
IBM2 citations72
US11645208B2May 9, 2023
Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
IBM1 citations62
US11119932B2Sep 14, 2021
Operation of a multi-slice processor implementing adaptive prefetch control
IBM0 citations62
US5625631AApr 29, 1997
Pass through mode for multi-chip-module die
IBM5 citations62
US11157415B2Oct 26, 2021
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations61
US11093248B2Aug 17, 2021
Prefetch queue allocation protection bubble in a processor
IBM0 citations61
US11481219B2Oct 25, 2022
Store prefetches for dependent loads in a processor
IBM0 citations60
US10331566B2Jun 25, 2019
Operation of a multi-slice processor implementing adaptive prefetch control
IBM0 citations52
US10318419B2Jun 11, 2019
Flush avoidance in a load store unit
IBM0 citations52
US10191845B2Jan 29, 2019
Prefetch performance
IBM0 citations52
US10963249B2Mar 30, 2021
Processor prefetcher mode governor for switching between prefetch modes
IBM0 citations51
US10534715B2Jan 14, 2020
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations51
US11301386B2Apr 12, 2022
Dynamically adjusting prefetch depth
IBM0 citations50
US11163683B2Nov 2, 2021
Dynamically adjusting prefetch depth
IBM0 citations50
US11556475B2Jan 17, 2023
Power optimized prefetching in set-associative translation lookaside buffer structure
IBM0 citations49
US10936505B2Mar 2, 2021
Methods and systems for verifying out-of-order page fault detection
IBM0 citations45