Inventor
TUNG SHIH-HSIUNG S
US15 patents
⚠️ This page may combine multiple inventors who share the name “TUNG SHIH-HSIUNG S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS10324856B2Jun 18, 2019
Address translation for sending real address to memory subsystem in effective address based load-store unit
IBM14 citations85
US10417002B2Sep 17, 2019
Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
IBM9 citations84
US10310988B2Jun 4, 2019
Address translation for sending real address to memory subsystem in effective address based load-store unit
IBM13 citations84
US7949859B2May 24, 2011
Mechanism for avoiding check stops in speculative accesses while operating in real mode
IBM13 citations84
US7370177B2May 6, 2008
Mechanism for avoiding check stops in speculative accesses while operating in real mode
IBM15 citations84
US10977047B2Apr 13, 2021
Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
IBM5 citations73
US5319761AJun 7, 1994
Directory look-aside table for a virtual storage system including means for minimizing synonym entries
IBM13 citations70
US11157415B2Oct 26, 2021
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations61
US10318419B2Jun 11, 2019
Flush avoidance in a load store unit
IBM0 citations52
US10824494B2Nov 3, 2020
Operation of a multi-slice processor implementing exception handling in a nested translation environment
IBM0 citations51
US10664275B2May 26, 2020
Speeding up younger store instruction execution after a sync instruction
IBM0 citations51
US10534715B2Jan 14, 2020
Operation of a multi-slice processor implementing a unified page walk cache
IBM0 citations51
US10042691B2Aug 7, 2018
Operation of a multi-slice processor implementing exception handling in a nested translation environment
IBM0 citations51