Inventor

YAO CHIH-WEI

US30 patents

⚠️ This page may combine multiple inventors who share the name “YAO CHIH-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YAO CHIH-WEI

SAMSUNG ELECTRONICS CO LTD

Communication system with frequency synthesis mechanism and method of operation thereof

Sigma-delta modulation quantization error reduction technique for fractional-N phase-locked loop (PLL)

System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)

System and method for time-to-digital converter fine-conversion using analog-to-digital converter (ADC)

System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL)

System and method for providing fast-settling quadrature detection and correction

System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC)

System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)

Ring voltage controlled oscillator (VCO) startup helper circuit

Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit

Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition

System and method for calibrating pulse width and delay

System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to-digital converter (TDC)

Hybrid source-series termination driver with constant output swing

System and method for providing fast-settling quadrature detection and correction

Synchronous sampling in-phase and quadrature-phase (I/Q) detection circuit

Fine tuning control for a digitally controlled oscillator

Apparatus and method for automatic search of sub-sampling phase locked loop (SS-PLL) locking acquisition

System and method for fast-converging digital-to-time converter (DTC) gain calibration for DTC-based analog fractional-N phase lock loop (PLL)

Fine tuning control apparatus and method

System and method using temperature tracking for a controlled oscillator

MARVELL WORLD TRADE LTD

Reference clock compensation for fractional-N phase lock loops (PLLS)

Reference clock compensation for fractional-N phase lock loops (PLLs)

MARVELL INT LTD

High resolution sampling-based time to digital converter

Circuit and circuit methods for reduction of PFD noise contribution for ADPLL

YAO CHIH-WEI

Reference clock compensation for fractional-N phase lock loops (PLLs)

Circuit and circuit method for reduction of PFD noise contribution for ADPLL

GAO XIANG

High resolution sampling-based time to digital converter

PENTOMICS INC

Low phase-noise oscillator

WATANABE HIROSHI

Simulation method of an electron device