Inventor

KARDA KAMAL M

US150 patents

⚠️ This page may combine multiple inventors who share the name “KARDA KAMAL M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KARDA KAMAL M

MICRON TECHNOLOGY INC

Memory cells

Transistors and methods of forming transistors

Field effect transistor constructions and memory arrays

Memory device having 2-transistor vertical memory cell and shared channel region

Memory device having 2-transistor memory cell and access line plate

Semiconductor devices, hybrid transistors, and related methods

Memory cells and arrays of elevationally-extending strings of memory cells

Integrated assemblies having ferroelectric transistors with body regions coupled to carrier reservoirs

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Apparatuses having memory cells with two transistors and one capacitor, and having body regions of the transistors coupled with reference voltages

Memory cells

Field effect transistor constructions with gate insulator having local regions radially there-through that have different capacitance at different circumferential locations relative to a channel core periphery

Memory cells

Transistors and methods of forming transistors

Memory cells

Transistors and methods of forming transistors

Field effect transistor constructions and memory arrays

Multi-bit ferroelectric memory device and methods of forming the same

Vertical access device and apparatuses having a body connection line, and related method of operating the same

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith

Memory device having 2-transistor memory cell and access line plate

Semiconductor devices and hybrid transistors

Vertical 2-transistor memory cell

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor memory cell and access line plate

Semiconductor devices, hybrid transistors, and related methods

Memory device having 2-transistor vertical memory cell and separate read and write gates

Memory device having 2-transistor vertical memory cell and a common plate

Channel conduction in semiconductor devices

Gate-all-around floating-gate field effect memory transistor constructions including ferroelectric gate insulator

Memory device having 2-transistor vertical memory cell and shield structures

Memory device having 2-transistor vertical memory cell and a common plate

Devices including vertical transistors, and related methods and electronic systems

Memory device having 2-transistor vertical memory cell and shield structures

Self-aligned etch back for vertical three dimensional (3D) memory

Memory device having 2-transistor vertical memory cell and wrapped data line structure

Metal insulator semiconductor (MIS) contact in three dimensional (3D) vertical memory

Channel formation for vertical three dimensional (3D) memory

Vertical three-dimensional memory with vertical channel

Array of vertical transistors and method used in forming an array of vertical transistors

Array of recessed access gate lines

Integrated assemblies

Method of forming an array of vertical transistors

Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Memory device having shared access line for 2-transistor vertical memory cell

Memory cells

Vertical 3D single word line gain cell with shared read/write bit line

GUHA JAYDIP

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith