Inventor

PANGAL KIRAN

US84 patents

⚠️ This page may combine multiple inventors who share the name “PANGAL KIRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANGAL KIRAN

INTEL CORP

Use of error correction pointers to handle errors in memory

Recovery algorithm in non-volatile memory

Dynamic window to improve NAND endurance

Dual trench isolation using single critical lithographic patterning

Methods and apparatus to reduce threshold voltage drift

Apparatus and method for drift cancellation in a memory

Techniques associated with a read and write window budget for a two level memory system

Reduced uncorrectable memory errors

Cross-point memory single-selection write technique

Cross point memory control

Transient current-protected threshold switching devices systems and methods

Cross-point memory single-selection write technique

Managing disturbance induced errors

Reduced uncorrectable memory errors

Dual trench isolation using single critical lithographic patterning

Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Techniques for adaptive moving read references for memory cell read error recovery

Techniques to mitigate bias drift for a memory device

Integrated setback read with reduced snapback disturb

Threshold voltage expansion

Set and reset operation in phase change memory and associated techniques and configurations

Mitigating read disturb in a cross-point memory

Multi-level cell (MLC) cross-point memory

Transient current-protected threshold switching devices systems and methods

Method and apparatus for reducing silent data errors in non-volatile memory systems

Error correction in memory

Cross-point memory single-selection write technique

Reduced uncorrectable memory errors

Transient current-protected threshold switching devices systems and methods

Phase change memory current

Managing disturbance induced errors

Single-bit first error correction

Error correction in non—volatile memory

Multistage memory cell read

Refresh of data stored in a cross-point non-volatile memory

Thermal-disturb mitigation in dual-deck cross-point memories

Scaling factors for hard decision reads of codewords distributed across die

Multi-level cell (MLC) techniques and circuits for cross-point memory

Multistage set procedure for phase change memory

Provision of holding current in non-volatile random access memory

Multistage set procedure for phase change memory

Provision of holding current in non-volatile random access memory

GUO XIN

Cycling endurance extending for memory cells of a non-volatile memory array

Defect management in memory systems

MICRON TECHNOLOGY INC

Methods and apparatuses for modulating threshold voltages of memory cells

Modified write voltage for memory devices

UNIV PRINCETON

Micro-mechanical probes for charge sensing

GULIANI SANDEEP

Multistage memory cell read

PANGAL KIRAN

Dynamic window to improve NAND endurance

WAKCHAURE YOGESH B

Extended select gate lifetime