Inventor

ROSS JONATHAN K

US27 patents

⚠️ This page may combine multiple inventors who share the name “ROSS JONATHAN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROSS JONATHAN K

HEWLETT PACKARD DEVELOPMENT CO

Partially virtualizing an I/O device for use by virtual machines

Processor-architecture for facilitating a virtual machine monitor

Multiprocessor system with interactive synchronization of local clocks

Method and apparatus for performing critical tasks using speculative operations

Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system

Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads

Method and apparatus for managing access to out-of-frame registers

Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes

Method and apparatus for managing access to out-of-frame registers

Mapping an active entry within a hashed page table

INST THE DEV OF EMERGING ARCHI

Method and apparatus for calculating a page table index from a virtual address

Method and apparatus for managing access to out-of-frame Registers

Apparatus and method for a virtual hashed page table

Computer architecture for the deferral of exceptions on speculative instructions

Method and apparatus for pre-validating regions in a virtual addressing scheme

Method and apparatus for transferring data between a register stack and a memory resource

Method and apparatus for pre-validating regions in a virtual addressing scheme

IDEA CORP

Method and apparatus for executing a flush RS instruction to synchronize a register stack with instructions executed by a processor

LOADRS instruction and asynchronous context switch

Cover instruction and asynchronous backing store switch

Code sequence for asynchronous backing store switch utilizing both the cover and LOADRS instructions

HEWLETT PACKARD CO

Apparatus and method for a virtual hashed page table

Emulated branch effected by trampoline mechanism

INTEL CORP

Software and hardware-managed translation lookaside buffer

IDEA CORP OF DELAWARE

System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor&#39;s execution of instructions during a state saving context switch

HEWLETT PACKARD DEVELOPMENT LP

Reducing latency, when accessing task priority levels

ROSS JONATHAN K

In-processor dynamic address redirection table for substituting instruction strings

System and method for synchronizing a register stack engine (RSE) and backing memory image with a processor's execution of instructions during a state saving context switch