Inventor

SAIR SULEYMAN

US25 patents

⚠️ This page may combine multiple inventors who share the name “SAIR SULEYMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAIR SULEYMAN

INTEL CORP

Vector friendly instruction format and execution thereof

Providing vector horizontal compare functionality within a vector register

Fault tolerance and detection by replication of input data and evaluating a packed data execution result

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Efficient zero-based decompression

Apparatus and method of mask permute instructions

Instruction and logic to provide vector horizontal majority voting functionality

Packed rotate processors, methods, systems, and instructions

Vector friendly instruction format and execution thereof

Instructions and logic for blend and permute operation sequences

OULD-AHMED-VALL ELMOUSTAPHA

Instruction and logic to provide stride-based vector load-op functionality with mask duplication

Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering

Efficient zero-based decompression

Instruction and logic to provide vector horizontal majority voting functionality

Packed rotate processors, methods, systems, and instructions

Instruction and logic to provide vector loads with strides and masking functionality

Apparatus and method of mask permute instructions

Providing vector horizontal compare functionality within a vector register

Vector frequency compress instruction

SAIR SULEYMAN

Vector instruction for presenting complex conjugates of respective complex numbers

System, apparatus and method for generating a loop alignment count or a loop alignment mask

OULD AHMED VALL ELMOUSTAPHA

Vector frequency expand instruction

Systems, apparatuses, and method for strided access