Inventor

TOLL BRET L

US136 patents

⚠️ This page may combine multiple inventors who share the name “TOLL BRET L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TOLL BRET L

INTEL CORP

Systems, methods, and apparatuses for dot production operations

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for tile diagonal

Method and apparatus for power mode transition in a multi-thread processor

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for tile load

Systems, methods, and apparatuses for zeroing a matrix

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatus for matrix move

Systems, methods, and apparatuses for tile broadcast

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Systems, methods, and apparatus for tile configuration

Method and apparatus for combining micro-operations to process immediate data

Method and apparatus for decompressing relative addresses

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Packed data element predication processors, methods, systems, and instructions

Zeroing a cache line

Packed data element predication processors, methods, systems, and instructions

Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode

Vector friendly instruction format and execution thereof

Rotate instructions that complete execution without reading carry flag

Add instructions to add three source operands

Systems, methods, and apparatuses for matrix add, subtract, and multiply

Method and apparatus for power mode transition in a multi-thread processor

Systems, methods, and apparatuses for tile store

Systems, methods, and apparatuses for dot production operations

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for tile load, multiplication and accumulation

Systems, methods, and apparatuses for tile matrix multiplication and accumulation

Systems, methods, and apparatuses for tile transpose

Systems, methods, and apparatuses for matrix operations

Rotate instructions that complete execution either without writing or reading flags

Apparatus and method of improved packed integer permute instruction

Cache allocation with code and data prioritization

Floating point round-off amount determination processors, methods, systems, and instructions

Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register

OULD-AHMED-VALL ELMOUSTAPHA

Efficient zero-based decompression

Apparatus and method for shuffling floating point or integer values

Instruction execution that broadcasts and masks data values at different levels of granularity

Packed rotate processors, methods, systems, and instructions

GOPAL VINODH

Add instructions to add three source operands

Rotate instructions that complete execution without reading carry flag

HUGHES CHRISTOPHER J

Gathering and scattering multiple data elements

TOLL BRET L

Systems, apparatuses, and methods for performing mask bit compression

OULD AHMED VALL ELMOUSTAPHA

Instruction and logic to provide conversions between a mask register and a general purpose register or memory