Inventor
VAN NGO MINH
US13 patents
⚠️ This page may combine multiple inventors who share the name “VAN NGO MINH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ADVANCED MICRO DEVICES INC
11 patentsUS6153523ANov 28, 2000
Method of forming high density capping layers for copper interconnects with improved adhesion
ADVANCED MICRO DEVICES INC90 citations97
US6764951B1Jul 20, 2004
Method for forming nitride capped Cu lines with reduced hillock formation
ADVANCED MICRO DEVICES INC67 citations95
US7071086B2Jul 4, 2006
Method of forming a metal gate structure with tuning of work function by silicon incorporation
ADVANCED MICRO DEVICES INC32 citations92
US6406996B1Jun 18, 2002
Sub-cap and method of manufacture therefor in integrated circuit capping layers
ADVANCED MICRO DEVICES INC16 citations92
US5963841AOct 5, 1999
Gate pattern formation using a bottom anti-reflective coating
ADVANCED MICRO DEVICES INC45 citations92
US6297148B1Oct 2, 2001
Method of forming a silicon bottom anti-reflective coating with reduced junction leakage during salicidation
ADVANCED MICRO DEVICES INC18 citations83
US6472336B1Oct 29, 2002
Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material
ADVANCED MICRO DEVICES INC9 citations74
US6989601B1Jan 24, 2006
Copper damascene with low-k capping layer and improved electromigration reliability
ADVANCED MICRO DEVICES INC5 citations73
US6429141B1Aug 6, 2002
Method of manufacturing a semiconductor device with improved line width accuracy
ADVANCED MICRO DEVICES INC7 citations73
US6329718B1Dec 11, 2001
Method for reducing stress-induced voids for 0.25mμ and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby
ADVANCED MICRO DEVICES INC12 citations72
US6492258B1Dec 10, 2002
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY
ADVANCED MICRO DEVICES INC3 citations61