Inventor
BAIR DEAN G
US18 patents
⚠️ This page may combine multiple inventors who share the name “BAIR DEAN G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
17 patentsUS6119219ASep 12, 2000
System serialization with early release of individual processor
IBM98 citations97
US6079013AJun 20, 2000
Multiprocessor serialization with early release of processors
IBM76 citations95
US6865645B1Mar 8, 2005
Program store compare handling between instruction and operand caches
IBM27 citations92
US10061679B2Aug 28, 2018
Evaluating fairness in devices under test
IBM4 citations83
US10055327B2Aug 21, 2018
Evaluating fairness in devices under test
IBM4 citations83
US10289512B2May 14, 2019
Persistent command parameter table for pre-silicon device testing
IBM1 citations71
US9892010B2Feb 13, 2018
Persistent command parameter table for pre-silicon device testing
IBM2 citations71
US9619312B2Apr 11, 2017
Persistent command parameter table for pre-silicon device testing
IBM2 citations71
US7996203B2Aug 9, 2011
Method, system, and computer program product for out of order instruction address stride prefetch performance verification
IBM2 citations62
US6560687B1May 6, 2003
Method of implementing a translation lookaside buffer with support for a real space control
IBM4 citations62
US9524801B2Dec 20, 2016
Persistent command parameter table for pre-silicon device testing
IBM2 citations61
US7213122B2May 1, 2007
Controlling the generation and selection of addresses to be used in a verification environment
IBM2 citations58
US10678670B2Jun 9, 2020
Evaluating fairness in devices under test
IBM0 citations51
US10671506B2Jun 2, 2020
Evaluating fairness in devices under test
IBM0 citations51
US9990290B2Jun 5, 2018
Cache coherency verification using ordered lists
IBM0 citations47
US9665280B2May 30, 2017
Cache coherency verification using ordered lists
IBM0 citations47
US9665281B2May 30, 2017
Cache coherency verification using ordered lists
IBM0 citations47