Inventor

SCHLUESSLER TRAVIS

US56 patents

⚠️ This page may combine multiple inventors who share the name “SCHLUESSLER TRAVIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SCHLUESSLER TRAVIS

INTEL CORP

Cross validation of data using multiple subsystems

Signed manifest for run-time verification of software program identity and integrity

Roaming secure authenticated network access method and apparatus

Agent presence monitor configured to execute in a secure environment

System and method for adapting executable object to a processing unit

High-speed resume for GPU applications

Asynchronous execution mechanism

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

Generating and communicating information on locations of program sections in memory

Systems and methods for host virtual memory reconstitution

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

Leveraging control surface fast clears to optimize 3D operations

GPU mixed primitive topology type processing

System and method for adapting executable object to a processing unit

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Method and apparatus for subdividing shader workloads in a graphics processor for efficient machine configuration

Systems and methods for secure host resource management

High-speed resume for GPU applications

Dynamic cache control mechanism

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Leveraging control surface fast clears to optimize 3D operations

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Asynchronous execution mechanism

Workload scheduling and distribution on a distributed graphics device

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Unified architecture for BVH construction based on hardware pre-sorting and a parallel, reconfigurable clustering array

GPU mixed primitive topology type processing

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Workload scheduling and distribution on a distributed graphics device

Speculative execution of hit and intersection shaders on programmable ray tracing architectures

System and method for adapting executable object to a processing unit

Multi-tile memory management mechanism

Position-based rendering apparatus and method for multi-die/GPU graphics processing

Multi-tile memory management mechanism

Position-based rendering apparatus and method for multi-die/GPU graphics processing

Position-based rendering apparatus and method for multi-die/GPU graphics processing

3D graphics driver to split frames into multiple command buffer submissions based on analysis of previous frames

Apparatus and method for acceleration data structure refit

Apparatus and method for acceleration data structure refit

High vertex count geometry work distribution for multi-tile GPUs

High performance constant cache and constant access mechanisms

Architecture and system for host management

Tile-based multiple resolution rendering of images

Leveraging control surface fast clears to optimize 3D operations

GPU register allocation mechanism

DURHAM DAVID M

Method and apparatus for run-time in-memory patching of code from a service processor

SCHLUESSLER TRAVIS

Signed manifest for run-time verification of software program identity and integrity

DURHAM DAVID

Cross validation of data using multiple subsystems