P

Inventor

LIN HWONG-KWO

US26 patents
⚠️ This page may combine multiple inventors who share the name “LIN HWONG-KWO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NVIDIA CORP

25 patents
US7839170B1Nov 23, 2010

Low power single rail input voltage level shifter

NVIDIA CORP20 citations92
US7643330B1Jan 5, 2010

Sequentially-accessed 1R/1W double-pumped single port SRAM with shared decoder architecture

NVIDIA CORP40 citations91
US7626878B1Dec 1, 2009

Active bit line charge keeper

NVIDIA CORP27 citations91
US9183922B2Nov 10, 2015

Eight transistor (8T) write assist static random access memory (SRAM) cell

NVIDIA CORP11 citations84
US7768320B1Aug 3, 2010

Process variation tolerant sense amplifier flop design

NVIDIA CORP9 citations84
US7463065B1Dec 9, 2008

Low power single-rail-input voltage level shifter

NVIDIA CORP10 citations84
US9542992B2Jan 10, 2017

SRAM core cell design with write assist

NVIDIA CORP9 citations83
US8866528B2Oct 21, 2014

Dual flip-flop circuit

NVIDIA CORP7 citations81
US9355710B2May 31, 2016

Hybrid approach to write assist for memory array

NVIDIA CORP15 citations80
US9110141B2Aug 18, 2015

Flip-flop circuit having a reduced hold time requirement for a scan input

NVIDIA CORP4 citations70
US10672461B2Jun 2, 2020

Write assist negative bit line voltage generator for SRAM array

NVIDIA CORP3 citations69
US7830175B1Nov 9, 2010

Low power single-rail-input voltage level shifter

NVIDIA CORP4 citations63
US7649762B1Jan 19, 2010

Area efficient high performance memory cell

NVIDIA CORP4 citations63
US7583126B2Sep 1, 2009

Apparatus and method for preventing current leakage when a low voltage domain is powered down

NVIDIA CORP6 citations63
US7772885B1Aug 10, 2010

Level shifter circuit to shift signals from a logic voltage to an input/output voltage

NVIDIA CORP2 citations61
US7492204B1Feb 17, 2009

Generic flexible timer design

NVIDIA CORP6 citations61
US9484115B1Nov 1, 2016

Power savings via selection of SRAM power source

NVIDIA CORP2 citations60
US9219480B2Dec 22, 2015

Low tau synchronizer flip-flop with dual loop feedback approach to improve mean time between failure

NVIDIA CORP0 citations52
US9842631B2Dec 12, 2017

Mitigating external influences on long signal lines

NVIDIA CORP0 citations51
US8988123B2Mar 24, 2015

Small area low power data retention flop

NVIDIA CORP1 citations51
US9390788B2Jul 12, 2016

Configurable delay circuit and method of clock buffering

NVIDIA CORP0 citations49
US9123438B2Sep 1, 2015

Configurable delay circuit and method of clock buffering

NVIDIA CORP0 citations49
US9525401B2Dec 20, 2016

Low clocking power flip-flop

NVIDIA CORP1 citations48
US7504872B2Mar 17, 2009

Generic flexible timer design

NVIDIA CORP0 citations40
US10181842B2Jan 15, 2019

Mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion

NVIDIA CORP0 citations38

YANG JUN

1 patent