Inventor
MARELLI ALESSIA
IT29 patents
⚠️ This page may combine multiple inventors who share the name “MARELLI ALESSIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICHELONI RINO
5 patentsUS8694855B1Apr 8, 2014
Error correction code technique for improving read stress endurance
MICHELONI RINO72 citations98
US8656257B1Feb 18, 2014
Nonvolatile memory controller with concatenated error correction codes
MICHELONI RINO69 citations98
US8621318B1Dec 31, 2013
Nonvolatile memory controller with error detection for concatenated error correction codes
MICHELONI RINO113 citations98
US8707122B1Apr 22, 2014
Nonvolatile memory controller with two-stage error correction technique for enhanced reliability
MICHELONI RINO46 citations94
US8694849B1Apr 8, 2014
Shuffler error correction code system and method
MICHELONI RINO51 citations94
MICROSEMI STORAGE SOLUTIONS (US) INC
5 patentsUS9450610B1Sep 20, 2016
High quality log likelihood ratios determined using two-index look-up table
MICROSEMI STORAGE SOLUTIONS (US) INC55 citations94
US9590656B2Mar 7, 2017
System and method for higher quality log likelihood ratios in LDPC decoding
MICROSEMI STORAGE SOLUTIONS (US) INC26 citations93
US9454414B2Sep 27, 2016
System and method for accumulating soft information in LDPC decoding
MICROSEMI STORAGE SOLUTIONS (US) INC25 citations93
US9448881B1Sep 20, 2016
Memory controller and integrated circuit device for correcting errors in data read from memory cells
MICROSEMI STORAGE SOLUTIONS (US) INC16 citations92
US9417804B2Aug 16, 2016
System and method for memory block pool wear leveling
MICROSEMI STORAGE SOLUTIONS (US) INC11 citations84
IP GEM GROUP LLC
4 patentsUS9799405B1Oct 24, 2017
Nonvolatile memory system with read circuit for performing reads using threshold voltage shift read instruction
IP GEM GROUP LLC44 citations94
US10291263B2May 14, 2019
Auto-learning log likelihood ratio
IP GEM GROUP LLC14 citations86
US10157677B2Dec 18, 2018
Background reference positioning and local reference positioning using threshold voltage shift read
IP GEM GROUP LLC14 citations84
US10283215B2May 7, 2019
Nonvolatile memory system with background reference positioning and local reference positioning
IP GEM GROUP LLC12 citations83
PMC SIERRA US INC
4 patentsUS9235467B2Jan 12, 2016
System and method with reference voltage partitioning for low density parity check decoding
PMC SIERRA US INC28 citations94
US9128858B1Sep 8, 2015
Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values
PMC SIERRA US INC47 citations94
US9092353B1Jul 28, 2015
Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system
PMC SIERRA US INC33 citations94
US8990661B1Mar 24, 2015
Layer specific attenuation factor LDPC decoder
PMC SIERRA US INC37 citations94
MICROSEMI SOLUTIONS U S INC
2 patentsMICRON TECHNOLOGY INC
2 patentsUS10630317B2Apr 21, 2020
Method for performing error corrections of digital information codified as a symbol sequence
MICRON TECHNOLOGY INC0 citations51
US8347201B2Jan 1, 2013
Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code
MICRON TECHNOLOGY INC0 citations49