Inventor

JUN KIMIN

US78 patents

Patents

50 patents

US10797139B2Oct 6, 2020

Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)

INTEL CORP15 citations84

US10043797B2Aug 7, 2018

Techniques for forming vertical transistor architectures

INTEL CORP7 citations84

US12199018B2Jan 14, 2025

Direct bonding in microelectronic assemblies

INTEL CORP2 citations75

US12107060B2Oct 1, 2024

Microelectronic assemblies with inductors in direct bonding regions

INTEL CORP5 citations75

US12062631B2Aug 13, 2024

Microelectronic assemblies with inductors in direct bonding regions

INTEL CORP4 citations74

US12176323B2Dec 24, 2024

Microelectronic assemblies

INTEL CORP2 citations73

US11676966B2Jun 13, 2023

Stacked transistors having device strata with different channel widths

INTEL CORP2 citations73

US11658221B2May 23, 2023

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP3 citations73

US11640961B2May 2, 2023

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

INTEL CORP2 citations73

US11393777B2Jul 19, 2022

Microelectronic assemblies

INTEL CORP2 citations73

US11393818B2Jul 19, 2022

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

INTEL CORP2 citations73

US11348897B2May 31, 2022

Microelectronic assemblies

INTEL CORP3 citations73

US10784358B2Sep 22, 2020

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP3 citations73

US10700039B2Jun 30, 2020

Silicon die with integrated high voltage devices

INTEL CORP5 citations73

US10453679B2Oct 22, 2019

Methods and devices integrating III-N transistor circuitry with Si transistor circuitry

INTEL CORP2 citations73

US10186484B2Jan 22, 2019

Metal on both sides with clock gated-power and signal routing underneath

INTEL CORP4 citations73

US11244943B2Feb 8, 2022

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

INTEL CORP2 citations72

US10490449B2Nov 26, 2019

Techniques for revealing a backside of an integrated circuit device, and associated configurations

INTEL CORP1 citations72

US10439057B2Oct 8, 2019

Multi-gate high electron mobility transistors and methods of fabrication

INTEL CORP3 citations72

US12417978B2Sep 16, 2025

Microelectronic assemblies having backside die-to-package interconnects

INTEL CORP0 citations63

US12406956B2Sep 2, 2025

Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers

INTEL CORP0 citations63

US12300579B2May 13, 2025

Liquid cooled interposer for integrated circuit stack

INTEL CORP0 citations63

US12288810B2Apr 29, 2025

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP0 citations63

US11935933B2Mar 19, 2024

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP0 citations63

US12463180B2Nov 4, 2025

Monolithic chip stacking using a die with double-sided interconnect layers

INTEL CORP0 citations62

US12362325B2Jul 15, 2025

Monolithic chip stacking using a die with double-sided interconnect layers

INTEL CORP0 citations62

US12100762B2Sep 24, 2024

Wrap-around source/drain method of making contacts for backside metals

INTEL CORP0 citations62

US12100761B2Sep 24, 2024

Wrap-around source/drain method of making contacts for backside metals

INTEL CORP0 citations62

US11996404B2May 28, 2024

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

INTEL CORP0 citations62

US11869894B2Jan 9, 2024

Metallization structures for stacked device connectivity and their methods of fabrication

INTEL CORP0 citations62

US11854894B2Dec 26, 2023

Integrated circuit device structures and double-sided electrical testing

INTEL CORP0 citations62

US11784165B2Oct 10, 2023

Monolithic chip stacking using a die with double-sided interconnect layers

INTEL CORP0 citations62

US11721649B2Aug 8, 2023

Microelectronic assemblies

INTEL CORP0 citations62

US11594452B2Feb 28, 2023

Techniques for revealing a backside of an integrated circuit device, and associated configurations

INTEL CORP0 citations62

US11552104B2Jan 10, 2023

Stacked transistors with dielectric between channels of different device strata

INTEL CORP0 citations62

US11532719B2Dec 20, 2022

Transistors on heterogeneous bonding layers

INTEL CORP0 citations62

US11482621B2Oct 25, 2022

Vertically stacked CMOS with upfront M0 interconnect

INTEL CORP0 citations62

US11430814B2Aug 30, 2022

Metallization structures for stacked device connectivity and their methods of fabrication

INTEL CORP0 citations62

US10896847B2Jan 19, 2021

Techniques for revealing a backside of an integrated circuit device, and associated configurations

INTEL CORP0 citations62

US10763248B2Sep 1, 2020

Multi-layer silicon/gallium nitride semiconductor

INTEL CORP1 citations61

Showing the top 50 of 78 patents by PatentIndex Score.

JUN KIMIN

Patents

Methods of forming backside self-aligned vias and structures formed thereby

Monolithic three-dimensional (3D) ICs with local inter-level interconnects

Integrated circuit structures

Backside contact structures and fabrication for metal on both sides of devices

Fabrication and use of through silicon vias on double sided interconnect device

Wrap-around source/drain method of making contacts for backside metals

Fabrication and use of through silicon vias on double sided interconnect device

Monolithic chip stacking using a die with double-sided interconnect layers

Methods of forming backside self-aligned vias and structures formed thereby

Monolithic three-dimensional (3D) ICs with local inter-level interconnects

Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)

Techniques for forming vertical transistor architectures

Direct bonding in microelectronic assemblies

Microelectronic assemblies with inductors in direct bonding regions

Microelectronic assemblies with inductors in direct bonding regions

Microelectronic assemblies

Stacked transistors having device strata with different channel widths

Backside contact structures and fabrication for metal on both sides of devices

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Microelectronic assemblies

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Microelectronic assemblies

Backside contact structures and fabrication for metal on both sides of devices

Silicon die with integrated high voltage devices

Methods and devices integrating III-N transistor circuitry with Si transistor circuitry

Metal on both sides with clock gated-power and signal routing underneath

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

Techniques for revealing a backside of an integrated circuit device, and associated configurations

Multi-gate high electron mobility transistors and methods of fabrication

Microelectronic assemblies having backside die-to-package interconnects

Bilayer memory stacking with computer logic circuits shared between bottom and top memory layers

Liquid cooled interposer for integrated circuit stack

Backside contact structures and fabrication for metal on both sides of devices

Backside contact structures and fabrication for metal on both sides of devices

Monolithic chip stacking using a die with double-sided interconnect layers

Monolithic chip stacking using a die with double-sided interconnect layers

Wrap-around source/drain method of making contacts for backside metals

Wrap-around source/drain method of making contacts for backside metals

Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material

Metallization structures for stacked device connectivity and their methods of fabrication

Integrated circuit device structures and double-sided electrical testing

Monolithic chip stacking using a die with double-sided interconnect layers

Microelectronic assemblies

Techniques for revealing a backside of an integrated circuit device, and associated configurations

Stacked transistors with dielectric between channels of different device strata

Transistors on heterogeneous bonding layers

Vertically stacked CMOS with upfront M0 interconnect

Metallization structures for stacked device connectivity and their methods of fabrication

Techniques for revealing a backside of an integrated circuit device, and associated configurations

Multi-layer silicon/gallium nitride semiconductor