Inventor

BALLUCHI DANIELE

IT103 patents

⚠️ This page may combine multiple inventors who share the name “BALLUCHI DANIELE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BALLUCHI DANIELE

MICRON TECHNOLOGY INC

Host-resident translation layer write command associated with logical block to physical address of a memory device

Memory controller for managing data and error information

Operational modes for reduced power consumption in a memory system

Apparatuses and methods for variable latency memory operations

Data state synchronization

Apparatuses and methods for variable latency memory operations

Apparatuses and methods for variable latency memory operations

Apparatuses and methods for performing multiple memory operations

Command queuing

Controller for managing multiple types of memory

Caching or evicting host-resident translation layer based on counter

Command queuing

Timing parameter adjustment mechanisms

Logical to physical table fragments

Apparatuses and methods for counter update operations

Hybrid memory system interface

Command queuing

Latency-based storage in a hybrid memory system

Apparatuses and methods for counter update operations

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Data relocation in hybrid memory

Logical to physical table fragments

Memory operations on data

Memory management

Apparatuses and methods for performing multiple memory operations

CRC raid recovery from hard failure in memory systems

Memory bank protection

Memory address translation for data protection and recovery

Apparatus for redundant array of independent disks

CRC RAID recovery from hard failure in memory systems

Adjustable memory cell reliability management

Strategic memory cell reliability management

Controllers and methods for accessing memory devices via multiple modes

Log management maintenance operation and command

Data stripe protection

Memory bank protection

Memory operations on data

Maintenance command interfaces for a memory system

Hybrid memory system interface

Operational modes for reduced power consumption in a memory system

Modified parity data using a poison data unit

Timing parameter adjustment mechanisms

Maintenance command interfaces for a memory system

ST MICROELECTRONICS SRL

Redundancy scheme for a memory integrated circuit

Column decoder circuit for page reading of a semiconductor memory

BALLUCHI DANIELE

Controlling clock input buffers

Non-volatile memory circuit, system, and method

VILLA CORRADO

Method and devices for controlling power loss

CONFALONIERI EMANUELE

Temperature alert and low rate refresh for a non-volatile memory