Inventor

WANG SHENG-HSIUNG

TW39 patents

⚠️ This page may combine multiple inventors who share the name “WANG SHENG-HSIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG SHENG-HSIUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

System and method of processing cutting layout and example switching circuit

Method and IC design with non-linear power rails

Method of forming layout design

Semiconductor device and method of manufacturing semiconductor device

Cell layout and structure

Integrated circuit having angled conductive feature

Method and IC design with non-linear power rails

Methods for reducing contact depth variation in semiconductor fabrication

System and method of processing cutting layout and example switching circuit

FinFET having a relaxation prevention anchor

Semiconductor device and manufacturing method thereof

Integrated circuit with elongated coupling

Standard cell design with dummy padding

Integrated circuit having angled conductive feature

Semiconductor device including a conductive feature over an active region

Semiconductor device including a conductive feature over an active region

Integrated circuit having angled conductive feature

Methods for reducing contact depth variation in semiconductor fabrication

Interconnect structures and methods of fabrication thereof

Method and IC design with non-linear power rails

Space optimization between SRAM cells and standard cells

Interconnect structures and methods of fabrication thereof

Method and IC design with non-linear power rails

Methods for reducing contact depth variation in semiconductor fabrication

Cell layout and structure

FinFET having a relaxation prevention anchor and related methods

Methods for reducing contact depth variation in semiconductor fabrication

Semiconductor device structure with dielectric dummy gate and method for forming the same

Method of forming a FinFET having a relaxation prevention anchor

Semiconductor device including a conductive feature over an active region

Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device

Integrated circuit with elongated coupling

Cell layout and structure

Via rail structure

TAIWAN SEMICONDUCTOR MFG

Method of forming layout design

Hard mask removal for semiconductor devices

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

HUANG YU-LIEN

Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure

WANG SHENG-HSIUNG

Fabrication methods of integrated semiconductor structure