Inventor
MADDURI VENKATESWARA
US30 patents
⚠️ This page may combine multiple inventors who share the name “MADDURI VENKATESWARA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
28 patentsUS10224954B1Mar 5, 2019
Floating point to fixed point conversion
INTEL CORP48 citations98
US10656942B2May 19, 2020
Fixed point to floating point conversion
INTEL CORP29 citations94
US11256504B2Feb 22, 2022
Apparatus and method for complex by complex conjugate multiplication
INTEL CORP11 citations86
US10705839B2Jul 7, 2020
Apparatus and method for multiplying, summing, and accumulating sets of packed bytes
INTEL CORP9 citations84
US10223114B1Mar 5, 2019
Fixed point to floating point conversion
INTEL CORP8 citations84
US11243765B2Feb 8, 2022
Apparatus and method for scaling pre-scaled results of complex multiply-accumulate operations on packed real and imaginary data elements
INTEL CORP2 citations73
US11074073B2Jul 27, 2021
Apparatus and method for multiply, add/subtract, and accumulate of packed data elements
INTEL CORP5 citations73
US10763891B2Sep 1, 2020
Floating point to fixed point conversion
INTEL CORP3 citations73
US10664270B2May 26, 2020
Apparatus and method for vector multiply and accumulate of unsigned doublewords
INTEL CORP6 citations73
US10514924B2Dec 24, 2019
Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
INTEL CORP2 citations73
US12346695B2Jul 1, 2025
Copy a subset of status flags from a control and status register to a flags register
INTEL CORP0 citations62
US11809867B2Nov 7, 2023
Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
INTEL CORP0 citations62
US11755323B2Sep 12, 2023
Apparatus and method for complex by complex conjugate multiplication
INTEL CORP0 citations62
US11573799B2Feb 7, 2023
Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
INTEL CORP0 citations62
US10977039B2Apr 13, 2021
Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
INTEL CORP0 citations62
US10552154B2Feb 4, 2020
Apparatus and method for multiplication and accumulation of complex and real packed data elements
INTEL CORP1 citations62
US10514923B2Dec 24, 2019
Apparatus and method for vector multiply and accumulate of signed doublewords
INTEL CORP1 citations62
US10318298B2Jun 11, 2019
Apparatus and method for shifting quadwords and extracting packed words
INTEL CORP1 citations62
US11249754B2Feb 15, 2022
Apparatus and method for vector horizontal add of signed/unsigned words and doublewords
INTEL CORP0 citations52
US10802826B2Oct 13, 2020
Apparatus and method for performing dual signed and unsigned multiplication of packed data elements
INTEL CORP0 citations52
US12204903B2Jan 21, 2025
Dual sum of quadword 16×16 multiply and accumulate
INTEL CORP0 citations51
US10795676B2Oct 6, 2020
Apparatus and method for multiplication and accumulation of complex and real packed data elements
INTEL CORP0 citations42
US10664277B2May 26, 2020
Systems, apparatuses and methods for dual complex by complex conjugate multiply of signed words
INTEL CORP0 citations42
US10496407B2Dec 3, 2019
Apparatus and method for adding packed data elements with rotation and halving
INTEL CORP0 citations42
US10496403B2Dec 3, 2019
Apparatus and method for left-shifting packed quadwords and extracting packed doublewords
INTEL CORP0 citations42
US10481910B2Nov 19, 2019
Apparatus and method for shifting quadwords and extracting packed words
INTEL CORP0 citations42
US10768896B2Sep 8, 2020
Apparatus and method for processing fractional reciprocal operations
INTEL CORP0 citations40
US10664237B2May 26, 2020
Apparatus and method for processing reciprocal square root operations
INTEL CORP0 citations40