Inventor
RAO VENKATA N S N
US22 patents
⚠️ This page may combine multiple inventors who share the name “RAO VENKATA N S N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INVECAS INC
11 patentsUS10061340B1Aug 28, 2018
Bandgap reference voltage generator
INVECAS INC53 citations91
US10498564B2Dec 3, 2019
Receiver for handling high speed transmissions
INVECAS INC10 citations81
US9971975B2May 15, 2018
Optimal data eye for improved Vref margin
INVECAS INC7 citations80
US10014866B2Jul 3, 2018
Clock alignment scheme for data macros of DDR PHY
INVECAS INC2 citations72
US9444463B2Sep 13, 2016
Voltage level shifter
INVECAS INC4 citations72
US9715907B1Jul 25, 2017
Optimal data eye for improved Vref margin
INVECAS INC5 citations69
US10094859B1Oct 9, 2018
Voltage detector
INVECAS INC2 citations68
US10502769B2Dec 10, 2019
Digital voltmeter
INVECAS INC0 citations51
US9954538B2Apr 24, 2018
Clock alignment scheme for data macros of DDR PHY
INVECAS INC0 citations51
US10361684B2Jul 23, 2019
Duty cycle detection
INVECAS INC0 citations46
US9716492B1Jul 25, 2017
Method and circuit for duty cycle detection
INVECAS INC0 citations41
KOOL CHIP INC
6 patentsUS9564905B2Feb 7, 2017
Methods and systems for clocking a physical layer interface
KOOL CHIP INC4 citations82
US9467149B2Oct 11, 2016
Methods and systems for distributing clock and reset signals across an address macro
KOOL CHIP INC4 citations82
US9337846B2May 10, 2016
Methods and systems for determining whether a receiver is present on a PCI-express bus
KOOL CHIP INC0 citations50
US9286260B2Mar 15, 2016
Serial-to parallel converter using serially-connected stages
KOOL CHIP INC1 citations50
US8952737B2Feb 10, 2015
Methods and systems for calibration of a delay locked loop
KOOL CHIP INC0 citations41
US9349421B2May 24, 2016
Memory interface
KOOL CHIP INC0 citations40