Inventor

LAI WEI-AN

TW39 patents

⚠️ This page may combine multiple inventors who share the name “LAI WEI-AN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LAI WEI-AN

TAIWAN SEMICONDUCTOR MFG CO LTD

Manufacturing method for semiconductor device

Semiconductor devices having power rails and signal tracks arranged in different layer

Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same

Layout designs of integrated circuits having backside routing tracks

Hybrid power rail structure

Local interconnect structure

Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same

Backside signal interconnection

Hybrid fin field-effect transistor cell structures and related methods

Three dimensional integrated circuit with monolithic inter-tier vias (MIV)

Three dimensional integrated circuit with monolithic inter-tier vias (MIV)

Semiconductor devices and methods of manufacturing thereof

Semiconductor devices and methods of manufacturing thereof

Methods for generating a circuit with high density routing layout

Deep lines and shallow lines in signal conducting paths

Variable width nano-sheet field-effect transistor cell structure

Layout designs of integrated circuits having backside routing tracks

Backside signal interconnection

Hybrid fin field-effect transistor cell structures and related methods

Manufacturing method for semiconductor device

Memory device and layout, manufacturing method of the same

Semiconductor device having more similar cell densities in alternating rows

Multiple fin height integrated circuit

Hybrid fin field-effect transistor cell structures and related methods

Apparatus and methods for generating a circuit with high density routing layout

Method for routing local interconnect structure at same level as reference metal line

Layout designs of integrated circuits having backside routing tracks

Deep lines and shallow lines in signal conducting paths

Method of forming semiconductor device having more similar cell densities in alternating rows

Memory device and layout, manufacturing method of the same

Semiconductor devices and methods of manufacturing thereof

Semiconductor device and manufacturing method thereof

Variable width nano-sheet field-effect transistor cell structure

Multiple fin height integrated circuit

Integrated circuit with backside interconnections and method of making same

Structure and method for tying off dummy gate in semiconductor device

Backside conducting lines in integrated circuits

Integrated circuit, system and method of forming the same

MACRONIX INT CO LTD

Memory utilizing bundle-level status values and bundle status circuits